Gaurav G. Mehta

Reducing power in high-performance microprocessors

Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is outstripping the benefits of voltage reduction and feature size scaling. Designers are thus continuously challenged to come up with innovative ways to reduce power, while trying to meet all the other constraints imposed on the design. This paper presents an overview of the issues related to power consumption in the context of Intel CPUs. The main trends that are driving the increased focus on design for low power are described. System and benchmarking issues, and sources of power consumption in a high-performance CPU are briefly described. Techniques that have been tried on real designs in the past are described. The role of CAD tools and their limitations in this domain are also discussed. In addition, areas that need increased research focus in the future are also pointed out.

Profile-driven program synthesis for evaluation of system power dissipation

This paper presents a new approach for estimatingpower dissipation in a high performance microprocessor chip.First, characteristic profile (including parameters such as thecache miss rate, branch prediction miss rate, pipeline stalls,instruction mix, memory references, etc.) is extracted fromapplication programs. Then, mixed integer linear programmingand heuristic rules are used to gradually transform a genericprogram template to into a fully functional program. Thesynthesized program exhibits the same performance and powerdissipation behavior (as characterized by the extracted profile),yet it has an instruction trace orders of magnitude smaller thanthe initial trace. The synthesized program is subsequentlysimulated on a register-transfer level description of the targetmicroprocessor to provide the power dissipation value. Resultsobtained for the Intels Pentium processor executing standardbenchmark programs show a simulation time reduction by 3-5orders of magnitude.

Fully automated physical implementation methodology for Tolapai-the first IA based SoC

The integration of today¿s complex multi-power domain IOs, inherited from legacy ¿Reuse IP¿ sources, poses a big challenge to the full chip physical integration in terms of product cost and design cycle time for products such as Tolapai, the first IA based SoC with IA CPU core, South bridge (ICH), North bridge (MCH), acceleration hardware and networking interfaces. To meet these challenges, the Tolapai design team created the Intel® first fully automated physical implementation methodology that accomplished a 28 percent reduction in the final design convergence cycle from RTL freeze to tape-out with about 20 percent fewer design resources over the entire project. The methodology features a fully automated ASIC implementation method for integrating multi-power well IO blocks, high speed block, and a ¿Correct by Construction¿ solution for the deep sub-micron technology challenges such as strict via density and double via rule on the wide metal without introducing new DRC violations. The automation provides quick turn-around of the several iterations required to achieve performance verification and final convergence while requiring no mask design resources.

An Improved ASIC/SOC Design Methodology for Quick Design Convergence

An improved ASIC/SOC design methodology for quick design convergence is described in this paper. Unlike the conventional ASIC/SOC design methodologies focused on automation, our new methodology focuses on streamlining the ASIC/SOC flows timing consuming steps by applying our experts BKMs (best known methodology) to accelerate design convergence. It enabled us to shorten the time consuming phases dramatically with relatively minimal efforts. This resulted in smooth execution across different phases of the design and enabled us to meet the aggressive tape-out schedule