Sudarshan Kumar

Gate-clocked domino circuits with reduced leakage current

Positive feedback circuit for fast domino logic

Fast static CMOS adder

Method and apparatus for reducing soft errors in dynamic circuits

MOS adder with minimum pass gates in carry line

Carry skip adder with enhanced grouping scheme

Low power entry latch to interface static logic with dynamic logic

LOW POWER PRECHARGE SCHEME FOR MEMORY BIT LINES

Method and apparatus for low power memory bit line precharge

Method and apparatus for providing a high speed tristate buffer