Geert Vanmeerbeeck

MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures

Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.

An industrial design space exploration framework for supporting run-time resource management on multi-core systems

Current multi-core design methodologies are facing increasing unpredictability in terms of quality due to the actual diversity of the workloads that characterize the deployment scenario. To this end, these systems expose a set of dynamic parameters which can be tuned at run-time to achieve a specified Quality of Service (QoS) in terms of performance. A run-time manager operating system module is in charge of matching the specified QoS with the available platform resources by manipulating the overall degree of task-level parallelism of each application as well as the frequency of operation of each of the system cores.

Automatic workload generation for system-level exploration based on modified GCC compiler

Future embedded system products, e.g. smart hand-held mobile terminals, will accommodate a large number of applications that will partly run sequentially and independently, partly concurrently and interacting on massively parallel computing platforms. Already for systems of moderate complexity, the design space will be huge and its exploration requires that the system architect is able to quickly evaluate the performances of candidate architectures and application mappings. The mainstream evaluation technique today is the system-level performance simulation of the applications and platforms using abstracted workload and processing capacity models, respectively. These virtual system models allow fast simulation of large systems at an early phase of development with reasonable modeling effort and time. The accuracy of the performance results is dependent on how closely the models used reflect the actual system. This paper presents a compiler based technique for automatic generation of workload models for performance simulation, while exploiting an overall approach and platform performance capacity models developed previously. The resulting workload models are experimented using x264 video and JPEG encoding application examples.

Virtual Java/FPGA interface for networked reconfiguration

A virtual interface between Java and FPGA for networked reconfiguration is presented. Through the Java/FPGA interface, Java applications can exploit hardware accelerators with FPGAs for both functional flexibility and performance acceleration. At the same time, the interface is platform independent. It enables the networked application developers to design their applications with only one interface in mind when considering the interfacing issues. The virtual interface is part of our work to build a platform-independent deployment framework for the networked services. In the framework, both the software and hardware components of services can be platform independently described and deployed.

SYSTEMC AND OCAPI-XL BASED SYSTEM-LEVEL DESIGN FOR RECONFIGURABLE SYSTEMS-ON-CHIP

Reconfigurability is becoming an important part of System-on-Chip (SoC) design to cope with the increasing demands for simultaneous flexibility and computational power. Current hardware/software co-design methodologies provide little support for dealing with the additional design dimension introduced. Further support at the system-level is needed for the identification and modeling of dynamically re-configurable function blocks, for efficient design space exploration, partitioning and mapping, and for performance evaluation. The over-head effects, e.g. context switching and configuration data, should be included in the modeling already at the system-level in order to produce credible information for decision-making. This chapter focuses on hardware/software codesign applied for reconfigurable SoCs. We discuss exploration of additional requirements due to reconfigurability, report extensions to two C++ based languages/methodologies, SystemC and OCAPI-xl, to support those requirements, and present results of three case studies in the wireless and multimedia communication domain that were used for the validation of the approaches.

Microscope-on-chip: combining lens-free microscopy with integrated photonics

Lens-free in-line Holographic Microscopy (LHM) is a promising imaging technique for many biomedical and industrial applications. The main advantage of the technique is the simplicity of the imaging hardware, requiring no lenses nor high-precision mechanical components. Nevertheless, the LHM systems achieve high imaging performance only in combination with a high-quality and complex illumination. Furthermore, to achieve truly high-throughput imaging capabilities, many applications require a complete on-chip integration. We demonstrate the strength, versatility and scalability of our integrated approach on two microscopes-on-chip instances that combine image sensor technologies with photonics (and micro-fluidics): a fully integrated Point-Source (PS) LHM module for in-flow cell inspection and Large Field-of-View (LFoV) microscope with on-chip photonic illumination for large-area imaging applications. The proposed PS-LHM module consists of a photonic illumination, a micro-fluidic channel and an imager, integrated in a total volume smaller than 0.5 mm3. A low-loss single-mode photonic waveguide is adapted to generate a high- NA illumination spot. Experimental results show strong focusing capabilities and sufficient overall coupling efficiency. Current PS-LHM prototype reaches imaging resolution below 600nm. Our LFoV-LHM system is extremely vertically compact as it consists of only one 1mm-thick illumination chip and one 3mm-thick imaging module. The illumination chip is based on fractal-layout phase-matched waveguides designed to generate multiple light sources that create a quasi-planar illumination wavefront over an area few square millimeter large. Current illumination prototype has active area of approximately 1.2×1.2mm2. Our LFoV-LHM prototype reaches imaging resolution of 870nm using image sensor with 1.12μm pixel pitch with maximum FoV of 16.47mm2.

Using neural networks for high-speed blood cell classification in a holographic-microscopy flow-cytometry system

High-throughput cell sorting with flow cytometers is an important tool in modern clinical cell studies. Most cytometers use biomarkers that selectively bind to the cell, but induce significant changes in morphology and inner cell processes leading sometimes to its death. This makes label-based cell sorting schemes unsuitable for further investigation. We propose a label-free technique that uses a digital inline holographic microscopy for cell imaging and an integrated, optical neural network for high-speed classification. The perspective of dense integration makes it attractive to ultrafast, large-scale cell sorting. Network simulations for a ternary classification task (monocytes/granulocytes/lymphocytes) resulted in 89% accuracy.

Lens-free digital in-line holographic imaging for wide field-of-view, high-resolution and real-time monitoring of complex microscopic objects

Lens-free inline Holographic Microscopy (LHM) holds great promise for biomedical and industrial applications thanks to its conceptual simplicity. However, the challenge lies in achieving an image quality comparable to conventional microscopes. We demonstrate a high-throughput LHM system that is able to resolve 1.23μm-thin lines on a standard USAF 1951 test target with 1.67μm pixels at the full field-of-view (>29mm2). The system is based on a unique multiwavelength iterative-phase-retrieval method, using customized hardware and real-time post-processing software. We have evaluated our system in experiments ranging from single-cell inspection to in-vitro imaging of stem-cell colonies.

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach

The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application.

Accurate label-free 3-part leukocyte recognition with single cell lens-free imaging flow cytometry

Three-part white blood cell differentials which are key to routine blood workups are typically performed in centralized laboratories on conventional hematology analyzers operated by highly trained staff. With the trend of developing miniaturized blood analysis tool for point-of-need in order to accelerate turnaround times and move routine blood testing away from centralized facilities on the rise, our group has developed a highly miniaturized holographic imaging system for generating lens-free images of white blood cells in suspension. Analysis and classification of its output data, constitutes the final crucial step ensuring appropriate accuracy of the system. In this work, we implement reference holographic images of single white blood cells in suspension, in order to establish an accurate ground truth to increase classification accuracy. We also automate the entire workflow for analyzing the output and demonstrate clear improvement in the accuracy of the 3-part classification. High-dimensional optical and morphological features are extracted from reconstructed digital holograms of single cells using the ground-truth images and advanced machine learning algorithms are investigated and implemented to obtain 99% classification accuracy. Representative features of the three white blood cell subtypes are selected and give comparable results, with a focus on rapid cell recognition and decreased computational cost.