Andy Lambrechts

Architecture exploration for a reconfigurable architecture template

Coarse-grained architectures (CGRAs) can be tailored and optimized for different application domains. The vast design space of coarse-grained reconfigurable architectures complicates the design of optimized processors. The goal is to design a domain-specific processor that provides just enough-flexibility for that domain while minimizing the energy consumption for a given level of performance. However, a flexible architecture template and a retargetable simulator and compiler enable systematic architecture exploration that can lead to more efficient domain-specific architecture design. This article presents such an environment and an architecture exploration for a novel CGRA template.

Distributed Loop Controller Architecture for Multi-threading in Uni-threaded VLIW Processors

Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has been proven to be one of the most power hungry parts of the system. This paper introduces an architectural enhancement for the instruction memory to reduce energy and improve performance. The proposed distributed instruction memory organization requires minimal hardware overhead and allows execution of multiple loops in parallel in a uni-processor system. This architecture enhancement can reduce the energy consumed in the instruction and data memory hierarchy by 70.01 % and improve the performance by 32.89% compared to enhanced SMT based architectures

A compact, high-speed, and low-cost hyperspectral imager

Although the potential of hyperspectral imaging has been demonstrated for several applications, using laboratory setups in research environments, its adoption by industry has so far been limited due to the lack of high speed, low cost and compact hyperspectral cameras. To bridge the gap between research and industry, we present a novel hyperspectral sensor that integrates a wedge filter on top of a standard CMOS sensor. To enable the low-cost processing of a microscopic wedge filter, we have introduced a design that is able to compensate for process variability. The result is a compact and fast hyperspectral camera made with low-cost CMOS process technology. The current prototype camera acquires 100 spectral bands over a spectral range from 560 nm to 1000 nm, with a spectral resolution better than 10 nm and a spatial resolution of 2048 pixels per line. The speed is 180 frames per second at illumination levels as typically used in machine vision. The prototype is a hyperspectral line scanner that acquires 16 lines per spectral band in parallel on a 4 MPixel sensor. The theoretic line rate for this implementation is thus 2880 lines per second.

A compact snapshot multispectral imager with a monolithically integrated per-pixel filter mosaic

The adoption of spectral imaging by industry has so far been limited due to the lack of high speed, low cost and compact spectral cameras. Moreover most state-of-the-art spectral cameras utilize some form of spatial or spectral scanning during acquisition, making them ill-suited for analyzing dynamic scenes containing movement. This paper introduces a novel snapshot multispectral imager concept based on optical filters monolithically integrated on top of a standard CMOS image sensor. It overcomes the problems mentioned for scanning applications by snapshot acquisition, where an entire multispectral data cube is sensed at one discrete point in time. This is enabled by depositing interference filters per pixel directly on a CMOS image sensor, extending the traditional Bayer color imaging concept to multi- or hyperspectral imaging without a need for dedicated fore-optics. The monolithic deposition leads to a high degree of design flexibility. This enables systems ranging from application-specific, high spatial resolution cameras with 1 to 4 spectral filters, to hyperspectral snapshot cameras at medium spatial resolutions and filters laid out in cells of 4x4 to 6x6 or more. Through the use of monolithically integrated optical filters it further retains the qualities of compactness, low cost and high acquisition speed, differentiating it from other snapshot spectral cameras.

Power breakdown analysis for a heterogeneous NoC platform running a video application

Users expect future handheld devices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on performance and power consumption and forces designers to optimize all parts of their platform. Evaluating the overall platform power breakdown is therefore critical to determine where to spend the efforts on power optimization. Surprisingly, few studies exist on that topic and decisions generally rely on common belief. We have realized a complete power breakdown for a realistic platform to identify the major power bottlenecks. This paper presents this power assessment of a realistic heterogeneous network on chip platform including processors, network and data/instruction memory hierarchy, running a video processing chain from camera to display. Our power breakdown identifies the main bottlenecks in the memory hierarchy and the foreground memory, and shows that global interconnect is not that critical for a well-optimized application mapping.

Coarse-Grained Reconfigurable Array Architectures

Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.

Very wide register: an asymmetric register file organization for low power embedded processors

In current embedded systems processors, multi-ported register files are one of the most power hungry parts of the processor, even when they are clustered. This paper presents a novel register file architecture, which has single ported cells and asymmetric interfaces to the memory and to the datapath. Several realistic kernels from the TI DSP benchmark and from software defined radio (SDR) are mapped on the architecture. A complete physical design of the architecture is done in TSMC 90nm technology. The novel architecture presented is shown to obtain energy gains of up to 10times with respect to conventional multi-ported register file over the different benchmarks

A snapshot multispectral imager with integrated tiled filters and optical duplication

Although the potential of spectral imaging has been demonstrated in research environments, its adoption by industry has so far been limited due to the lack of high speed, low cost and compact spectral cameras. We have previously presented work to overcome this limitation by monolithically integrating optical interference filters on top of standard CMOS image sensors for high resolution pushbroom hyperspectral cameras. These cameras require a scanning of the scene and therefore introduce operator complexity due to the need for synchronization and alignment of the scanning to the camera. This typically leads to problems with motion blur, reduced SNR in high speed applications and detection latency and overall restricts the types of applications that can use this system. This paper introduces a novel snapshot multispectral imager concept based on optical filters monolithically integrated on top of a standard CMOS image sensor. By using monolithic integration for the dedicated, high quality spectral filters at its core, it enables the use of mass-produced fore-optics, reducing the total system cost. It overcomes the problems mentioned for scanning applications by snapshot acquisition, where an entire multispectral data cube is sensed at one discrete point in time. This is achieved by applying a novel, tiled filter layout and an optical sub-system which simultaneously duplicates the scene onto each filter tile. Through the use of monolithically integrated optical filters it retains the qualities of compactness, low cost and high acquisition speed, differentiating it from other snapshot spectral cameras based on heterogeneously integrated custom optics. Moreover, thanks to a simple cube assembly process, it enables real-time, low-latency operation. Our prototype camera can acquire multispectral image cubes of 256x256 pixels over 32 bands in the spectral range of 600-1000nm at a speed of about 30 cubes per second at daylight conditions up to 340 cubes per second at higher illumination levels as typically used in machine vision applications.

Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor

Modern portable embedded devices provide continuously more features and need processors that are of increasingly higher performance in order to sustain very demanding multimedia and wireless applications. Larger amounts of flexibility need to be built in and the same processor needs to be used for a wide range of evolving products, while very strict energy constraints need to be met in order to provide a long battery life. Coarse Grained Reconflgurable Architectures (CGRAs) provide a mix of flexible computational resources and large amounts of programmable interconnect. However, this programmable interconnect is on average consuming about 50% of the cores energy consumpion for state of the art interconnection topologies. In this work we present an optimized interconnection implementation that selectively activates only the connections that are being used in a certain cycle, in order to reduce the energy spent in the interconnect. Using this optimization, we show the effect on the energy and performance trade-off for the ADRES CGRA. The energy cost of the optimized interconnect topologies that provide a higher performance can be reduced significantly, reducing the total energy consumption of the core with up to 40%. This will enable designers to develop more efficient architectures, tuned to a targeted application domain.

A CMOS-compatible, integrated approach to hyper- and multispectral imaging

Imec has developed a unique hyperspectral sensor concept in which the spectral unit is monolithically integrated on top of a standard CMOS sensor at wafer level, hence enabling the design of compact, low cost and high speed spectral cameras with a high design flexibility. This paper presents the various demonstrated prototype sensors, with different filter arrangements and performance, linked to different usage modes and application domains. It also reviews the key aspects and challenges of imecs hyperspectral technology.