Georg Vallant

Analog IQ impairments in Zero-IF radar receivers: Analysis, measurements and digital compensation

We address the Zero-IF or homodyne radio architecture as a pursuable way for small Radar receivers. While Zero-IF is beneficial for integration, several inherent analog impairments place a limit on the achievable dynamic range. The most dominant non-idealities are gain and phase imbalance in the IQ branches, mixer nonlinearity, and DC Offset. In the case of IQ Imbalance, careful receiver design can at best achieve an Image Rejection Ratio (IRR) of 30-40 dB. Also, IQ imbalance tends to be frequency-dependent with increasing bandwidth (BW). It has to be investigated, whether sophisticated digital post-processing is able to deliver a dynamic range sufficient for Pulse-Doppler Radar. After establishing some theoretical background and proposing digital correction methods, we will present hardware measurements of frequency-dependent IQ imbalance made on a Zero-IF receiver with large bandwidth. Despite significant improvements can be achieved using an offline calibration, time-varying drifts due to temperature changes will degrade the achievable IRR. Therefore adaptive circularity-based algorithms should be applied to track those changes. However, Radar Chirp signals at complex baseband (BB) cannot be used directly, as they are not circular. To restore the circularity for estimating the Complementary Autocorrelation Function (CACF), we propose applying a digital band-stop to the operational data beforehand. Highly increased IRR values are technically feasible: Digital Assistance acting jointly with state-of-the-art RF circuit design can pave the way for adequate performance in integrated receiver solutions.

2-channel Time-Interleaved ADC frequency response mismatch correction using adaptive I/Q signal processing

A novel adaptive compensation architecture for the frequency response mismatch of 2-channel Time-Interleaved ADC (TI-ADC) is proposed for developing high-yield self-adaptive systems. The proposed approach overcomes the existing methods in the sense that the TI-ADC mismatch identification can be performed without allocating a region where only the TI-ADC mismatch spurs are present. This is accomplished via mapping the TI-ADC problem into an I/Q mismatch problem which allows deploying complex statistical signal processing. As proof of the concept, the compensation architecture is demonstrated and tested on RF-sampling TI-ADC hardware data.

A blind frequency response mismatch correction algorithm for 4-channel Time-Interleaved ADC

A novel approach for the frequency response mismatch mitigation of a 4-channel Time-Interleaved ADC (TI-ADC) is proposed which enables the interleaving mismatch identification to be performed in a fully blind online manner. This is accomplished via generating an appropriate complex valued signal from the real valued TI-ADC output signal which allows deploying complex statistical signal processing methods for the mismatch identification in a manner similar to the I/Q imbalance correction. As proof of concept, the compensation architecture is implemented, demonstrated and tested using real RF-sampling 4-channel TI-ADC hardware data, evidencing spur reduction below 80 dBFS.

System-Level Mitigation of Undersampling ADC Nonlinearity for High-IF Radio Receivers

Abstract Over the last years ongoing advances in ADC technology have enabled RF signals to be sampled at IF frequencies. Undersampling is nowadays employed in software-defined radio or radar receivers and offers the possibility to relieve requirements in the analog receiver partition. Unfortunately, when moving to higher IF concepts, this becomes demanding for the ADC itself, because of inherent spurious-free dynamic range (SFDR) roll-off that increases with input frequency. This fact often limits the receivers IF placement to Nyquist zone (NZ) 2. In this work the emerging concept of Digital Assistance is pursued to give the receiver access to higher NZs while making no compromise on the SFDR. We will present and discuss post-correction results for two 16-bit high-speed converters from two different vendors at 120 and 125 MSPS, respectively. The proposed system-level post-correction decomposes nonlinearity into a static and a dynamic part. For both ADCs under investigation the degraded SFDR in higher NZs could be improved by up to 15 dB using purely digital linearization technologies, thus increasing the detectability of small signals in the presence of very strong signals or interferers. Near-identical results for both ADCs confirm the general validity of the system-level correction approach.