Wolfgang Schlecker

Analog IQ impairments in Zero-IF radar receivers: Analysis, measurements and digital compensation

We address the Zero-IF or homodyne radio architecture as a pursuable way for small Radar receivers. While Zero-IF is beneficial for integration, several inherent analog impairments place a limit on the achievable dynamic range. The most dominant non-idealities are gain and phase imbalance in the IQ branches, mixer nonlinearity, and DC Offset. In the case of IQ Imbalance, careful receiver design can at best achieve an Image Rejection Ratio (IRR) of 30-40 dB. Also, IQ imbalance tends to be frequency-dependent with increasing bandwidth (BW). It has to be investigated, whether sophisticated digital post-processing is able to deliver a dynamic range sufficient for Pulse-Doppler Radar. After establishing some theoretical background and proposing digital correction methods, we will present hardware measurements of frequency-dependent IQ imbalance made on a Zero-IF receiver with large bandwidth. Despite significant improvements can be achieved using an offline calibration, time-varying drifts due to temperature changes will degrade the achievable IRR. Therefore adaptive circularity-based algorithms should be applied to track those changes. However, Radar Chirp signals at complex baseband (BB) cannot be used directly, as they are not circular. To restore the circularity for estimating the Complementary Autocorrelation Function (CACF), we propose applying a digital band-stop to the operational data beforehand. Highly increased IRR values are technically feasible: Digital Assistance acting jointly with state-of-the-art RF circuit design can pave the way for adequate performance in integrated receiver solutions.

Frequency Response Mismatches in 4-channel Time-Interleaved ADCs: Analysis, Blind Identification, and Correction

This article proposes a novel adaptive architecture for blind identification and compensation of frequency response mismatches in 4-channel time-interleaved analog-to-digital-converters (TI-ADCs). Detailed frequency response mismatch modeling is first carried out elaborating in detail the interleaving mismatch spurs characteristics. Stemming from the established mirror-frequency crosstalk nature of the different mismatch spurs, the interleaving mismatch identification process is then carried out using complex second-order statistics based methods. The developed learning algorithm performs the mismatch identification and learns the mismatch compensation filter parameters in a blind manner for almost the full digital bandwidth of the 4 TI-ADC system. The proposed solutions efficiency and performance are verified and demonstrated using state-of-the-art RF-sampling TI-ADC hardware measurements with GHz range instantaneous bandwidth. In addition to this, the relationship between a four-channel TI-ADC and an I/Q sampling 2-channel TI-ADC is explored and an interesting link between the two is established in this work.

Analysis, Blind Identification, and Correction of Frequency Response Mismatch in Two-Channel Time-Interleaved ADCs

In this paper, novel blind identification and compensation architectures for the frequency response mismatch of a two-channel time-interleaved analog-to-digital-converter (TI-ADC) are proposed. First, detailed modeling of the frequency response mismatch is carried out, establishing a direct connection and similarity to the well-known in-phase/quadrature mismatch problem. Stemming from this modeling, the proposed blind mismatch identification and compensation architectures are then developed building on complex statistical signal processing. Compared to the existing methods in the literature, the proposed solutions can identify and correct the frequency response mismatch in a fully blind manner for the full digital bandwidth (BW) of the ADC system, and are also applicable in sub-sampling TI-ADC devices and RF sampling. The efficiency of the proposed solutions is verified and demonstrated using comprehensive measurements of actual RF-sampling TI-ADC hardware with gigahertz-scale instantaneous BW.

Digital full-band linearization of wideband direct-conversion receiver for radar and communications applications

This paper proposes a fully digital post-processing solution for cancelling nonlinear distortion and mirror-frequency interference in wideband direct-conversion receivers (DCRs). Favorable cost, integrability, and power efficiency have made DCRs a popular choice in communication systems. It is also an emerging trend in radar systems since digital post-processing enables sufficient performance. The proposed method cancels the most essential distortion adaptively during normal receiver operation without any prior information. Improved cancellation performance compared to the state-of-the-art is achieved considering inband and neighboring band distortion induced by the strong received signals. This is verified and demonstrated with extensive simulations and true RF hardware measurements.

Iterative FPGA Implementation Easing Safety Certification for Mixed-Criticality Embedded Real-Time Systems

The design and operation of an aircraft, a railway, and a nuclear power station that include either safety-critical or safety-related systems require a proof that its safety is assured. The process providing this proof is called certification. This paper suggests an iterative FPGA implementation and iterative certification concept for FPGA-based systems to provide design-time adaptability while the complexity is still kept low to ease certification. The practical evaluation of this concept demonstrates that reuse at implementation level of a previously implemented part is to 100% usable for iterative certification. Regarding the resource utilization and complexity, the evaluation shows that there are potential savings in resource utilization and complexity compared to conventional run-time configurable designs. Iterative certification reduces the recertification of a whole design to a recertification of the changed part only and a verification tool qualification. It is shown that tool qualification can be accomplished with relatively moderate effort. Therefore, the presented concept substantially eases the certification process when using modular design and building block reuse.

Low-complexity digital correction of 4-channel time-interleaved ADC frequency response mismatch using adaptive I/Q signal processing

This paper proposes a novel fully blind frequency response mismatches correction architecture for a four-channel time interleaved ADC (TI-ADC) using digital signal processing. By generating appropriate complex valued signals from the real valued TI-ADC output, a mapping of the TI-ADC problem into a mirror frequency interference problem is obtained, which allows using in-phase/quadrature (I/Q) mismatch correction techniques, e.g., circularity, for the frequency response mismatch identification. Compared to the existing methods in the literature, the proposed method allows for blind frequency response mismatch identification throughout the whole digital bandwidth and has substantially lower computational complexity while maintaining similar correction performance, hence making it suitable for an on-chip implementation. The compensation architecture is implemented, demonstrated and tested using real RF-sampling four-channel TI-ADC hardware data, achieving a multitone spur reduction below 80 dBFS.