George Goulas

A systematic two phase approach for the nurse rostering problem

Nurse rostering is an NP-hard combinatorial problem which makes it extremely difficult to efficiently solve real life problems due to their size and complexity. Usually real problem instances have complicated work rules related to safety and quality of service issues in addition to rules about quality of life of the personnel. For the aforementioned reasons computer supported scheduling and rescheduling for the particular problem is indispensable. The specifications of the problem addressed were defined by the First International Nurse Rostering Competition (INRC2010) sponsored by the leading conference in the Automated Timetabling domain, PATAT-2010. Since the competition imposed quality and time constraint requirements, the problem instances were partitioned into sub-problems of manageable computational size and were then solved sequentially using Integer Mathematical Programming. A two phase strategy was implemented where in the first phase the workload for each nurse and for each day of the week was decided while in the second phase the specific daily shifts were assigned. In addition, local optimization techniques for searching across combinations of nurses’ partial schedules were also applied. This sequence is repeated several times depending on the available computational time. The results of our approach and the submitted software produced excellent solutions for both the known and the hidden problem instances, which in respect gave our team the first position in all tracks of the INRC-2010 competition.

Design and implementation of an efficient integer count sort in CUDA GPUs

We describe experience on design and implementation of an efficient count sort algorithm on Compute Unified Device Architecture graphics processing units. The novelty of this work is twofold. At first, we propose a count sort algorithm for integers that needs no synchronization at its last step and thus, offers superior performance. At second, this work contributes ad hoc techniques for optimizing the performance of the algorithm on Compute Unified Device Architecture‐enabled graphics processing units. Copyright

Compiling Scilab to high performance embedded multicore systems

The mapping process of high performance embedded applications to todays multiprocessor system-on-chip devices suffers from a complex toolchain and programming process. The problem is the expression of parallelism with a pure imperative programming language, which is commonly C. This traditional approach limits the mapping, partitioning and the generation of optimized parallel code, and consequently the achievable performance and power consumption of applications from different domains. The Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of a Scilab-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from a high level of abstraction. The holistic solution of the ALMA toolchain allows the complexity of both the application and the architecture to be hidden, which leads to better acceptance, reduced development cost, and shorter time-to-market. Driven by the technology restrictions in chip design, the end of exponential growth of clock speeds and an unavoidable increasing request of computing performance, ALMA is a fundamental step forward in the necessary introduction of novel computing paradigms and methodologies.

Pursuit of better results for the examination timetabling problem using grid resources

Examination timetabling for universities is a difficult optimization problem with its main objective being to produce the best possible schedule for every student participating. Metaheuristics are a common way of coping with this problem mainly due to their flexibility in adapting to complex real world situations. In this contribution, Grid resources are exploited in order to locate solutions that might have been unreachable in a reasonable time using the processing power of a single computer.

Scheduling independent tasks on heterogeneous processors using heuristics and Column Pricing

Efficiently scheduling a set of independent tasks on a virtual supercomputer formed by many heterogeneous components has great practical importance, since such systems are commonly used nowadays. Scheduling efficiency can be seen as the problem of minimizing the overall execution time (makespan) of the set of tasks under question. This problem is known to be NP-hard and is currently addressed using heuristics, evolutionary algorithms and other optimization methods. In this paper, firstly, two novel fast executing heuristics, called LSufferage and TPB, are introduced. L(ist)Sufferage is based on the known heuristic Sufferage and can achieve in general better results than it for most of the cases. T(enacious)PB is also based on another heuristic (Penalty Based) and incorporates new ideas that significantly improve the quality of the resulted schedule. Secondly, a mathematical model of the problem is presented alongside with an associated approach based on the Linear Programming method of Column Pricing. This approach, which is called Column Pricing with Restarts (CPR), can be categorized as a hybrid mathematical programming and heuristic approach and is capable of solving in reasonable time problem instances of practically any size. Experiments show that CPR achieves superior results improving over published results on problem instances of various sizes. Moreover, hardware requirements of CPR are minimal.

PLEIADES: an internet-based parallel/distributed system

The use of LAN‐based clusters of computers for computational purposes has been in use for several years with significant success and acceptability. The introduction of the Internet infrastructure as the interconnection medium of the cluster allows for additional flexibility and transparency of such systems. PLEIADES is an Internet‐based parallel/distributed system whose purpose is to allow users to use distant computational resources in order to form virtual clusters. In addition, PLEIADES can be used as a computational infrastructure service provider for applications in need of computational resources. PLEIADES uses a tiered architecture with particular emphasis on the existence of a middle tier, whose task is to assist in the communication between the interface and the resource management tiers. The existence of the middle tier allows for the creation of an open system that is able to easily integrate with new resource management platforms and tools. Since the use of a mature resource management system for parallel/distributed computing was a prerequisite of the PLEIADES architecture, the Condor resource management environment was used. The design and implementation characteristics of PLEIADES together with some experimental uses of the system are also presented. Copyright

SchedSP: a Grid-based application service provider of scheduling solutions

In this paper, SchedSP, a middleware framework for providing scheduling solutions as services over the Internet, is presented. Emphasis is given on creating a reusable framework that facilitates the development of specialized clients for the input, output and control interfaces of the various scheduling applications. SchedSP manages the task of preparing and running the required processes and allows the application interface developer to focus on the functionality and efficiency of the interface. The Internet‐based scheduling applications created are competitive in all aspects with traditional locally executed applications. In this paper, detailed architecture and implementation details of the SchedSP framework prototype are presented. In addition, the methodology for creating specific case studies based on the SchedSP middleware framework is presented. Copyright

Solving the Examination Timetabling Problem in GPUs

The examination timetabling problem belongs to the class of combinatorial optimization problems and is of great importance for every University. In this paper, a hybrid evolutionary algorithm running on a GPU is employed to solve the examination timetabling problem. The hybrid evolutionary algorithm proposed has a genetic algorithm component and a greedy steepest descent component. The GPU computational capabilities allow the use of very large population sizes, leading to a more thorough exploration of the problem solution space. The GPU implementation, depending on the size of the problem, is up to twenty six times faster than the identical single-threaded CPU implementation of the algorithm. The algorithm is evaluated with the well known Toronto datasets and compares well with the best results found in the bibliography. Moreover, the selection of the encoding of the chromosomes and the tournament selection size as the population grows are examined and optimized. The compressed sparse row format is used for the conflict matrix and was proven essential to the process, since most of the datasets have a small conflict density, which translates into an extremely sparse matrix.

From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach

The mapping process of high performance embedded applications to todays multiprocessor system on chip devices suffers from a complex tool chain and programming process. The problem here is the expression of parallelism with a pure imperative programming language which is commonly C. This traditional approach limits the mapping, partitioning and the generation of optimized parallel code, and consequently the achievable performance and power consumption of applications from different domains. The Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of a Scilab-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from high level of abstraction. This holistic solution of the toolchain allows the complexity of both the application and the architecture to be hidden, which leads to a better acceptance, reduced development cost, and shorter time-to-market. Driven by the technology restrictions in chip design, the end of exponential growth of clock speeds, and an unavoidable increasing request of computing performance, ALMA is a fundamental step forward in the necessary introduction of novel computing paradigms and methodologies.

A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems

Todays reconfigurable multicore architectures become more and more complex. They consist of several processing units, not necessarily identical, different interconnecting modules, memories and possibly other components. Programming such kind of architectures requires deep knowledge of the underlying hardware and is thus very time consuming and error prone. On the other hand, automated tool chains that target multicore architectures are typically tailored to one specific architecture type and require a platform-specific programming model. Within the EU FP7 project Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) we address this shortcoming by a flexible tool chain featuring platform-independence on the architecture level as well as on the programming model. Thus, the tool chain is kept retarget able by using a novel architecture description language (ADL) for multiprocessor system on chip devices. Applications are expressed using the Scilab programming language allowing the end user to develop optimized programs without specific knowledge of the target architectures. Thereby, the ADL guides the code generation of the integrated tool flow through coarse- and fine grain parallelism extraction, parallel code optimizations and multicore simulations.