Kostas Masselos

System-level modeling of dynamically reconfigurable hardware with SystemC

To cope with the increasing demand for higher computational power and flexibility, dynamically reconfigurable blocks have become an important part inside a system-on-chip. Several methods have been proposed to incorporate their reconfiguration aspects into a design flow. They all lack either an interface to commercially available and industrially used tools or are restricted to a single vendor or technology environment. Therefore a methodology for modeling of dynamically reconfigurable blocks at the system-level using SystemC 2.0 is presented. The high-level model is based on a multi-context representation of the different functionalities that will be mapped on the reconfigurable block during different run-time periods. By specifying the estimated times of context-switching and active-running in the selected functionality modes, the methodology allows us to do true design space exploration at the system-level, without the need to map the design first to an actual technology implementation.

Strategy for power-efficient design of parallel systems

Application studies in the areas of image- and video-processing indicate that between 50%-80% of the power cost in these systems is due to data storage and transfers. This is especially true for multiprocessor realizations because conventional parallelization methods ignore the power cost and focus only on performance. However, the power consumption also heavily depends on the way a system is parallelized. To reduce this dominant cost, we propose to address the system-level storage organization for the multidimensional signals as a first step in mapping these applications, before the parallelization or partitioning decisions (in particular, before the hardware/software (HW/SW) partitioning, which is traditionally done too early in the design trajectory). Our methodology is illustrated on a parallel quadtree-structured difference pulse-code modulation video codec.

High-Level Cache Modeling for 2-D Discrete Wavelet Transform Implementations

The main implementations of the 2-D binary-tree discrete wavelet decomposition are theoretically analyzed and compared with respect to data-cache performance on instruction-set processor-based realizations. These implementations include various image-scanning techniques, from the classical row-column approach to the block-based and line-based methods, which are proposed in the framework of multimedia-coding standards. Analytical parameterized equations for the prediction of data-cache misses under general realistic assumptions are proposed. The accuracy and the consistency of the theory are verified through simulations on test platforms and a comparison is made with the results from a real platform.

System-Level Modeling of Dynamically Reconfigurable Co-processors

Dynamically reconfigurable co-processors (DRCs) are interesting design alternatives when both flexibility and performance are concerns. However, it is difficult to study the performance impact of including such devices into design when using traditional design methods and tools. In this paper, we present easily adaptable system-level techniques, which are able to perform fast exploration of different reconfiguration alternatives. A SystemC-based modeling method for DRCs and a high-level synthesis-based estimation tool to support system partitioning are presented.

Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures

A systematic approach for the assignment of array type data structures to the layers of fixed memory hierarchies present in instruction set processors is presented. Memory Hierarchy Layer Assignment (MHLA) is required to ensure the efficient exploitation of the data re-use present in multimedia type algorithms. Exploitation of data re-use through storage of the most frequently accessed and re-used data elements in the smaller levels of a processors physical memory hierarchy leads to significant execution time and power consumption savings. The proposed methodology for Memory Hierarchy Layer Assignment takes into consideration architectural features of the target processors such as the fixed physical data memory hierarchy and the hardware control mechanisms of some of the levels (caches) of the memory hierarchy. Experimental results prove that exploitation of data re-use combined with the proposed approach for Memory Hierarchy Layer Assignment leads to significant power consumption and performance gains.

Interaction between sub-word parallelism exploitation and low power code transformations for VLIW multi-media processors

In this paper, the main focus is on the interaction of power optimizing code transformations with the special performance improving sub-word instructions present in modern VLIW multimedia processors. The code transformations proposed by us heavily reduce the power consumption by moving the main part of the memory accesses from larger (off-chip) memories to smaller (on-chip) storage. In addition, most of the time their application also leads to system performance enhancement (in number of cycles) as well. Experimental results on real-life data-dominated applications clearly demonstrate that the application of our power optimizing code transformations approach is orthogonal to the use of instructions related to arithmetic (sub-word) parallelism exploitation. A second conclusion is that the positive impact of our transformations on performance is typically even larger than the effect of the sub-word instructions for the complete application.

SYSTEMC AND OCAPI-XL BASED SYSTEM-LEVEL DESIGN FOR RECONFIGURABLE SYSTEMS-ON-CHIP

Reconfigurability is becoming an important part of System-on-Chip (SoC) design to cope with the increasing demands for simultaneous flexibility and computational power. Current hardware/software co-design methodologies provide little support for dealing with the additional design dimension introduced. Further support at the system-level is needed for the identification and modeling of dynamically re-configurable function blocks, for efficient design space exploration, partitioning and mapping, and for performance evaluation. The over-head effects, e.g. context switching and configuration data, should be included in the modeling already at the system-level in order to produce credible information for decision-making. This chapter focuses on hardware/software codesign applied for reconfigurable SoCs. We discuss exploration of additional requirements due to reconfigurability, report extensions to two C++ based languages/methodologies, SystemC and OCAPI-xl, to support those requirements, and present results of three case studies in the wireless and multimedia communication domain that were used for the validation of the approaches.

Realization of wireless multimedia communication systems on reconfigurable platforms

Wireless multimedia communication systems become increasingly more computational intensive and demand for higher flexibility. The realization of these systems on reconfigurable hardware offers a good balance for these requirements. In this paper the suitability of commercially available reconfigurable hardware platforms for the target application domain is evaluated. Based on this evaluation a heterogeneous partly reconfigurable system-on-chip platform is identified as ideal implementation platform for the targeted systems. Systems from different target domains are analysed and different cases where the inclusion of reconfigurable hardware in their realizations would lead to improved quality in terms of implementation efficiency and flexibility are identified, Design methodology requirements for the realization of systems from the target application domain on the targeted platform are analysed and issues not covered by existing methodologies are identified. The principles of a methodology handling these open issues are described. Results from the prototyping of different systems are also presented and show the potentials of a reconfigurable hardware platform, which in the future will lead to reduced costs and increased flexibility of the wireless multimedia communication systems.

Compiling Scilab to high performance embedded multicore systems

The mapping process of high performance embedded applications to todays multiprocessor system-on-chip devices suffers from a complex toolchain and programming process. The problem is the expression of parallelism with a pure imperative programming language, which is commonly C. This traditional approach limits the mapping, partitioning and the generation of optimized parallel code, and consequently the achievable performance and power consumption of applications from different domains. The Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of a Scilab-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from a high level of abstraction. The holistic solution of the ALMA toolchain allows the complexity of both the application and the architecture to be hidden, which leads to better acceptance, reduced development cost, and shorter time-to-market. Driven by the technology restrictions in chip design, the end of exponential growth of clock speeds and an unavoidable increasing request of computing performance, ALMA is a fundamental step forward in the necessary introduction of novel computing paradigms and methodologies.

Low power synthesis of sum-of-products computation

Novel techniques for the power efficient synthesis of sum-of-product computations are presented. Simple and efficient heuristics for scheduling and assignment are described. Different partly static cost functions are proposed to drive the synthesis tasks. The proposed cost functions target the power consumption either in the buses connecting the functional units with the storage elements or inside the functional units. The partly static nature of the proposed cost functions reduces the time of the synthesis procedure. Experimental results from different relevant digital signal processing algorithmic kernels prove that the proposed synthesis techniques lead to significant power savings.