George K. C. Huang

Device-correlated metrology for overlay measurements

Abstract. One of the main issues with accuracy is the bias between the overlay (OVL) target and actual device OVL. In this study, we introduce the concept of device-correlated metrology (DCM), which is a systematic approach to quantify and overcome the bias between target-based OVL results and device OVL values. In order to systematically quantify the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking critical dimension scanning electron microscope (CD-SEM) target. The hybrid OVL target is designed to accurately represent the process influence on the actual device. In the general case, the CD-SEM can measure the bias between the target and device on the same layer after etch inspection (AEI) for all layers, the OVL between layers at AEI for most cases and after develop inspection for limited cases such as double-patterning layers. The results have shown that for the innovative process compatible hybrid targets the bias between the target and device is small, within the order of CD-SEM noise. Direct OVL measurements by CD-SEM show excellent correlation between CD-SEM and optical OVL measurements at certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for the imaging base OVL method using several target types advance imaging metrology, advance imaging metrology in die OVL, and the scatterometrybase OVL method. Future plans include broadening the hybrid target design to better mimic each layer process conditions such as pattern density. Additionally, for memory devices we are developing hybrid targets which enable other methods of accuracy verification.

High order correction and sampling strategy for 45nm immersion lithography overlay control

As advanced semiconductor companies move forward to the 45nm technology node, traditional overlay sampling and linear correction used in dry lithography become less feasible to bring overlay control into the desired budget. New overlay control methodologies need to be established to meet the needs of much tighter overlay budgets in the immersion lithography process. Overlay source of variance (SOV) was first investigated to understand the major contributor of overlay error sources. The SOVis broken down into wafer, field, and random components in order to utilize the SOV information to prioritize overlay improvement decisions. High order wafer level or field level error components are commonly observed as a significant contributor and requires attention to bring the overlay residual into the desired limit. Optimal sample is determined in considering sample plan robustness and throughput impact while increasing sampling becomes a necessity in 45nm technology node.

DCM: device correlated metrology for overlay measurements

One of the main issues with overlay error metrology accuracy is the bias between results based on overlay (OVL) targets and actual device overlay error. In this study, we introduce the concept of Device Correlated Metrology (DCM), which is a systematic approach to quantifying and overcoming the bias between target-based overlay results and device overlay issues. For systematically quantifying the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking CD-SEM (Critical Dimension – Scanning Electron Microscope) target. The hybrid OVL target is designed to accurately represent the process influence found on the real device. In the general case, the CD-SEM can measure the bias between target and device on the same layer at AEI (After Etch Inspection) for all layers, the OVL between layers at AEI for most cases and at ADI (After Develop Inspection) for limited cases such as DPL (Double Patterning Lithography). The results shown demonstrate that for the new process compatible hybrid targets the bias between target and device is small, of the order of CD-SEM measurement uncertainty. Direct OVL measurements by CD-SEM show excellent correlation with optical OVL measurements in certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for imaging based OVL metrology methods using AIM or AIMid OVL targets, and scatterometry-based overlay methods such as SCOL (Scatterometry OVL). Future plans include broadening the hybrid target design to better mimic each layer’s process conditions such as pattern density. We are also designing hybrid targets for memory devices.

Sampling strategy: optimization and correction for high-order overlay control for 45nm process node

The tight overlay budgets required for 45nm and beyond make overlay control a very important topic. With the adoption of immersion lithography, the incremental complexity brings much more difficulty to analyzing the source of variation and optimizing the sampling strategy. In this paper, there will be a discussion about how the use of an advanced sampling methodology and strategy can help to overcome this overlay control problem and insure sufficient overlay information to be captured for effective production lot excursion detection as well as rework decision making. There will also be a demonstration of the different correction methodologies to improve overlay control for dual-stage systems in order to maximize the productivity benef its with minimal impact to overlay performance.

Effects of laser bandwidth on tool to tool CD matching

According to the ITRS roadmap, low k1 imaging requires extremely tight control of Critical Dimension (CD). Maintaining the same performance from one exposure to another for new imaging requirements has become increasingly important, particularly for matching dry and wet systems. Tool to tool CD matching depends on many factors, for example, lens aberrations, partial coherence, laser spectral bandwidth and short range flare. We have performed a detailed study of laser bandwidth effects on tool CD matching for typical 65nm node structures exposed on immersion ArF scanners. A high accuracy on-board spectrometer was used to characterize the lithography Laser bandwidth, allowing measurements of both the FWHM and E95 parameters of the laser spectrum. Spectral bandwidth was adjusted over a larger range than normally experienced during wafer exposures using Cymers Tunable Advanced Bandwidth Stabilization device (T-ABS) to provide controlled changes in bandwidth while maintaining all other laser performance parameters within specification. Measurements of both Lines and Contact Holes on 65nm node structures through all pitches were made and correlated with bandwidth to determine the sensitivity of IDB and C/H to bandwidth variation. We demonstrated that bandwidth can be adjusted for CD matching on different tool using the T-ABS function.

KrF resists and process for implant layers at advanced nodes

The minimum design rule of device patterns for LSI implant layers has been shrinking constantly according to the industry requirements. Wavelength has been shortened and numerical aperture (NA) of the scanner has been enlarged to catch up with the required shrinkage. Implant layers are unique because the resist is nearly always used without an antireflective coating, and as a result, the resist is in direct contact with a multitude of substrate materials. In implant applications, the wafer topography sacrifices some of the lithographic performance in order to obtain adequate features on both top and bottom of the topography. KrF lithography has applied to most of the ion implant levels at todays advanced nodes. To solve the several issues in ion implant process, New KrF resist was designed specifically for the lithographic / implantation process requirements.

Manufacturing implementation of 32nm SRAM using ArF immersion with RET

As the pattern size shrinking down below 1/4 of the exposure wavelength, the NA of exposure tool has to be increased proportionally. The use of hyper NA and immersion exposure system for improving image quality may result in a small workable process window. Hence, resolution enhancement technology (RET) becomes a necessity for semiconductor manufacturing. Previous studies have demonstrated many RETs, such as CPL, DDL, IML and DPT etc. can improve the process window for different applications.1,2,3,4 In this work, we show manufacturing implementation of a 32nm node SRAM cell with different RET approaches. The diffusion, poly, contact, and metal layers were chosen as the target design. The process development project starts from the wafer exposure scheme setting, which includes the multi-exposure, illumination shape and mask type. After the RET has been specified, the process performance indexes, such as MEEF, PW, and CDU are characterized by using both simulation and empirical data. The mask design and OPC is implemented After the mask data preparation step, we then optimize exposure parameters for best printing performance and follow it by verifying actual wafer data. The mask making spec and DFM design rule constrains have been assessed and recommended for 32nm node manufacturing. Also, we have examined the immersion process defect impact and control methodology for production environment. In this paper, we report the result of optimizing RET process (including mask data generation, reticle making specifications, and wafer printing) for 32nm SRAM. With 193nm ultra high NA immersion exposure scanner (such as ASML /1900), it is capable of meeting 32nm SRAM manufacturing requirement.