George McNeil Lattimore

A 2 cycle 1 Mbit 4 way set associative 4 way interleave multi-processor L2 directory with array access/cycle 2.5 nsec

An experimental 2-cycle, 1-Mbit, 4-way set-associative, 4-way interleave, multiprocessor L2 directory with array access and cycle time equal to 2.5 ns is described. The directory function has three components: (1) address transmission and arbitration around a 17.3/spl times/17.3 chip (/spl sim/1/2 cycle), (2) directory array access (1 full cycle), and (3) tag compare (/spl sim/1/2 cycle). The directory array access design uses a combination of self-resetting and synchronous techniques that allow the array access to span 2 clock cycles even though the array can be pipelined at a single cycle frequency. The combination of synchronous techniques with self-resetting circuits allows the array cycle time to functionally change with the machine cycle time, yielding a greater sense-amplifier margin at longer cycles while maintaining the pipelining benefits of self-resetting circuitry. The process that the design is based upon is a 0.5-micron technology with a 0.25-micron effective gate length and 5 layers of metal. The SRAM cell size is 4.6/spl times/7.2 microns/sup 2/, a full 6-transistor cell with a single layer of poly, and a local area interconnect using a damascene tungsten process. The total directory area is 4 interleaves/spl times/5.6 mm/spl times/5.3 mm = 118.7 mm/sup 2/.