Georgios Vitzilaios

A Low-Power Wideband Reconfigurable Integrated Active-RC Filter With 73 dB SFDR

In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a reconfigurable transfer function (Chebyshev, Elliptic) and bandwidth (5 MHz, 10 MHz), is presented. The filter exploits digitally-controlled polysilicon resistor banks and a digital automatic tuning scheme to account for process and temperature variations. The operational amplifiers used are based on a new compensation technique that allows optimized high-frequency filter performance and minimized current consumption. A filter prototype has been fabricated in a 0.12-mum CMOS process, occupies 0.25 mm2 (tuning circuit included), and achieves an IIP3 of approximately +20 dBm, whereas its spurious free dynamic range (SFDR) reaches 73 dB. The dissipation of the filter core and the tuning circuit is 4.6 mW and 1.5 mW, respectively

A Low-Voltage 5-GHz Downconversion Mixer Employing A Second Harmonic Injection Linearization Technique

In this paper, a low-voltage CMOS mixer topology, appropriate for operation in the 5-GHz frequency band, is presented. The mixer combines several design techniques in order to achieve high linearity performance with minimum current consumption in a restricted 1-V supply. The proposed mixer utilizes an integrated transformer to improve the high frequency performance and to achieve large LO to RF isolation. In addition, a novel linearization technique based on second harmonic injection, is introduced to optimize linearity performance. The design is being implemented in a 0.13-mum CMOS technology.

Calculating distortion in active CMOS mixers using Volterra series

In this paper, an intermodulation distortion analysis for active CMOS mixers based on Volterra series theory is presented. As an outcome of the analysis, a software tool that facilitates a fast optimization of the mixers linearity performance has been developed. Results from the tool confirm excellent match with those obtained by popular commercial SPICE-like simulators, whereas simulation time is lowered by an order of magnitude

A 1-V, 5.5-GHz, CMOS LNA With Multiple Magnetic Feedback

A CMOS low-noise amplifier that utilizes multiple monolithic transformer magnetic feedback to simultaneously neutralize the gate-drain overlap capacitance of the amplifying transistor and achieve high gain at high frequencies when driving an on-chip capacitance is presented. The multiple transformer topology permits negative and positive feedback to be applied constructively, allowing for a stable design with adequate gain and large reverse isolation without noise figure (NF) degradation. Simulation results indicate voltage conversion gain of 17 dB, NF of 1.6 dB, and best-case third-order input intercept point of 13 dBm. The design is being implemented in a 0.13-mum CMOS technology

A 1-V 5-GHz CMOS Multiple Magnetic Feedback Receiver Front-End

In this paper, a receiver front-end module operating at 5 GHz and suitable for low-voltage operation is presented. The design consists of a single amplifying transistor low-noise amplifier topology that utilizes multiple magnetic feedback in order to simultaneously achieve high gain and high reverse isolation. In addition, a mixer topology for optimum performance regarding gain, noise, and linearity under low-voltage operation is presented. The design has been fabricated in IBMs 0.13-mum CMOS technology, and the measured performance indicates a receiver conversion gain of 22.3 dB, a noise figure of 2.64 dB, and a third-order input intercept point of .

A low-voltage CMOS LNA with multiple magnetic feedback for WLAN applications

A CMOS low-noise-amplifier (LNA) topology that utilizes multiple monolithic transformer magnetic feedback is presented. The proposed topology permits negative and positive feedback to be applied constructively, in order to simultaneously neutralize the gate-drain overlap capacitance of the amplifying transistor and achieve high gain at high frequencies when driving an on-chip capacitance. It also allows for a stable design with adequate gain and large reverse isolation without noise figure (NF) degradation. Simulation results indicate voltage conversion gain of 17 dB, NF of 1.6 dB and third-order input intercept point (IIP3) of 13 dBm. The design is being implemented in a 0.13 mum CMOS technology

Magnetic-Feedback-Based Predistortion Method for Low-Noise Amplifier Linearization

A predistortion method for CMOS low-noise amplifiers (LNAs) to be used in broadband wireless applications is presented. The method is based on the nulling of the third-order intermodulation distortion of the main amplifier by a highly nonlinear predistortion branch. Maximum nonlinearity product cancellation is ensured by a transformer feedback method. The technique improves linearity in a wide range of input power without significant gain and noise figure (NF) degradation. Simulation results on a 1-V LNA indicate a 10.3-dB improvement in the third-order input intercept point with a degradation of only 1 and 0.44 dB in amplifier gain and NF, respectively. The design is based on a 0.13-mum CMOS technology

A low-voltage, highly linear, integrated, active-RC filter

A 1-V, highly linear, integrated, active-RC, filter incorporating the ability to change both its transfer function (Chebyshev, elliptic) and its bandwidth (5 MHz, 10 MHz), is presented. The filter utilizes digitally controlled polysilicon resistor banks to account for variations of its corner frequency. A filter prototype, fabricated in a 0.12 /spl mu/m CMOS process, exhibits 20 dBm IIP3 and 73 dB SFDR, while dissipating only 4.6 mW.

A Magnetic Feedback Method for Low-Voltage CMOS LNA Reverse-Isolation Enhancement

A magnetic feedback method for enhancing the reverse isolation of low-voltage (1.2-V), single-transistor CMOS low-noise amplifiers (LNAs) is presented. The method neutralizes the gate-drain overlap capacitance of the amplifying transistor, allowing for adequate reverse isolation without gain reduction. The method does not require a differential LNA topology and input matching is facilitated since the degeneration inductor is not a part of a magnetic feedback loop. In addition, it allows for neutralizing the intrinsic part of the parasitic capacitance, which cannot be neglected in short-channel devices. Simulation results utilizing a standard 0.18-m CMOS process indicate a 17-29-dB improvement in the reverse-isolation performance with minimal noise figure deterioration.