Yannis Papananos

A Low-Power Wideband Reconfigurable Integrated Active-RC Filter With 73 dB SFDR

In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a reconfigurable transfer function (Chebyshev, Elliptic) and bandwidth (5 MHz, 10 MHz), is presented. The filter exploits digitally-controlled polysilicon resistor banks and a digital automatic tuning scheme to account for process and temperature variations. The operational amplifiers used are based on a new compensation technique that allows optimized high-frequency filter performance and minimized current consumption. A filter prototype has been fabricated in a 0.12-mum CMOS process, occupies 0.25 mm2 (tuning circuit included), and achieves an IIP3 of approximately +20 dBm, whereas its spurious free dynamic range (SFDR) reaches 73 dB. The dissipation of the filter core and the tuning circuit is 4.6 mW and 1.5 mW, respectively

Neural-network-based adaptive baseband predistortion method for RF power amplifiers

An adaptive baseband predistortion method for RF power amplifier (PA) linearization is proposed and experimentally demonstrated. The predistortion component is implemented by a single-input dual-output multilayer perceptron (MLP). Both amplitude-to-amplitude and amplitude-to-phase distortion products are compensated by backpropagation training of the neural network including the response of the PA. Effects of modulator and demodulator imperfections on system performance are examined. Measurements on a system prototype reveal a significant linearity improvement that reaches 25 dB.

Six-terminal MOSFET's: modeling and applications in highly linear, electronically tunable resistors

The electrical properties of a six-terminal MOSFET are studied and a strong-inversion model is derived. Due to its special structure, the six-terminal MOSFET can be operated as a highly-linear, electronically-tunable resistor. This is managed by applying proper voltages at the terminals of the structure, achieving channel uniformity independent of applied signals. Measurements on fabricated test devices yield distortion levels of -90 dB for 1 V/sub p-p/ signals.

Analysis of transconductances at all levels of inversion in deep submicron CMOS

This paper presents an in-depth analysis of transconductances in CMOS for advanced analog IC design. Transconductances in a 0.25 /spl mu/m CMOS technology have been measured over a large range of geometries and bias conditions. Gate (g/sub mg/), source (g/sub ms/), drain (g/sub md/) and bulk (g/sub mb/) transconductances are consistently normalized and represented vs. inversion coefficient (IC) from very weak to moderate and strong inversion. The ideal transconductance behavior in particular in weak inversion is analyzed via the analytical structure of the EKV MOSFET model. The new EKV 3.0 MOSFET model shows excellent abilities to correctly represent transconductances at all levels of inversion and channel lengths.

An Adjusted Constant-Current Method to Determine Saturated and Linear Mode Threshold Voltage of MOSFETs

The constant-current (CC) method uses a current criterion to determine the threshold voltage (VTH) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using the same current criterion in both saturation and linear modes leads to inconsistent results and incorrect interpretation of effects, such as drain-induced barrier lowering in advanced CMOS halo-implanted devices. The generalized adjusted CC method is based on the theory of the charge-based MOS transistor model. It introduces an adjusted current criterion, depending on VDS, allowing to coherently determine VTH for the entire range of VDS from linear operation to saturation. The method uses commonly available ID versus VG data with focus on moderate inversion. The method is validated with respect to the ideal surface potential model, and its suitability is demonstrated with technology-computer-aided-design data from a 65-nm CMOS technology and measured data from a 90-nm CMOS technology. Comparison with other widely used threshold voltage extraction methods is provided.

A comparative study of five integrator structures for monolithic continuous-time filters: a tutorial

Five integrator structures for IC filters are evaluated, i.e., the Gm-C integrator; the Gm-C-Opamp integrator; the Gm-C-OTA integrator; the MOSFET-C-Opamp integrator; and the MOSFET-C-OTA integrator. The advantages and disadvantages of each are presented based on several criteria. The main results of the comparison are provided in tabular form.<<ETX>>

A Low-Voltage Differentially Tuned Current-Adjusted 5.5-GHz Quadrature VCO in 65-nm CMOS Technology

A low-voltage low-phase-noise 5.5-GHz differential LC voltage-controlled oscillator (VCO) with quadrature outputs for direct and low intermediate frequency conversion is presented. The circuit is fully integrated in IBMs 65-nm radio-frequency complimentary metal-oxide-semiconductor process. Care has to be taken in achieving low phase noise, whereas the VCO core is powered from a low-voltage supply of 650 mV. The VCO incorporates a digitally controlled technique in order for the direct current to be adjusted in each oscillation band. Switching capacitors are adopted to enable the selection of the oscillating band, whereas differentially controlled varactors are used for fine tuning the circuit. Quadrature outputs are provided by two identical oscillators appropriately coupled. The oscillator has a wide tuning range, i.e., between 4.6 and 6.2 GHz (29%). The quadrature VCO core dissipates 8.71 mW from a voltage supply of 0.65 V, whereas its phase noise is -113 dBc/Hz at 1-MHz offset of a 5.5-GHz carrier. The whole circuit occupies 0.33 mm2 of die area.

Novel Si integrated inductor and transformer structures for RF IC design

Planar and 3D Si passive inductive structures are presented, with respect to their application in RF ICs. The modeling of the structures is realized by the use of a custom CAD tool, SISP. It Is shown how, for the first time, fast answers to complex questions can be obtained before fabrication, such as: inductance boost of up to 600% in three-layer spiral inductors compared to planar ones, with no cost in quality factor; optimization of the insertion and return losses of integrated transformers under area reduction schemes; modeling of practical integrated baluns; effect of physical separation on the crosstalk between inductors. The accuracy of modeling results is established through measurements in an array of fabricated structures.

A Low-Voltage 5-GHz Downconversion Mixer Employing A Second Harmonic Injection Linearization Technique

In this paper, a low-voltage CMOS mixer topology, appropriate for operation in the 5-GHz frequency band, is presented. The mixer combines several design techniques in order to achieve high linearity performance with minimum current consumption in a restricted 1-V supply. The proposed mixer utilizes an integrated transformer to improve the high frequency performance and to achieve large LO to RF isolation. In addition, a novel linearization technique based on second harmonic injection, is introduced to optimize linearity performance. The design is being implemented in a 0.13-mum CMOS technology.

Design of a Low Voltage-Low Power 3.1–10.6 GHz UWB RF Front-End in a CMOS 65 nm Technology

In this brief, the design of a 3.1 to 10.6 GHz ultra wideband (UWB) RF front-end (RFFE) is presented. It employs a novel low noise common gate amplifier combined with a noise canceling circuit, that provides wideband input matching, high voltage gain and low noise figure in the whole band of operation. It also adopts a passive single balanced direct conversion mixer with a custom designed balun at its local oscillator (LO) input. The RFFE achieves 20.6 dB of voltage gain and it has adequately flat frequency response. Its noise figure is 3-3.8 dB and the CP1 at the input is -19.7 dBm. The circuit consumes only 10.8 mW from a 1.2 V supply and it was designed in IBMs CMOS 65 nm process.