Gerald George Pechanek
Altera
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Publication
Featured researches published by Gerald George Pechanek.
international conference on asic | 2002
Gerald George Pechanek; Sergei Y. Larin; Thomas M. Conte
There exist a whole class of systems, which presents critical requirements for code density, efficient memory usage, low power and performance. A representative of this class are embedded DSP systems for SOC. This work presents a method for entropy-bounded encoding of an original ISA and decoupling it from a DSP core. The encoding allows the instruction storage to be used with high efficiency, which is only bounded by the information contents of an application, and relaxes any restrictions imposed on the ISA by the physical memory and branching mechanism. The concept is illustrated with an exemplary commercial DSP processor showing a reduction of the required instruction memory space of greater than 40% without significant impact on the instruction fetch stage of the DSP pipeline.
Archive | 2003
Thomas L. Drabenstott; Gerald George Pechanek; Edwin Franklin Barry; Charles W. Kurak
Archive | 1998
Gerald George Pechanek; Charles W. Kurak
Archive | 2001
Edwin Franklin Barry; Patrick R. Marchand; Gerald George Pechanek; Larry D. Larsen
Archive | 2005
Patrick R. Marchand; Gerald George Pechanek; Edward A. Wolff
Archive | 1999
Nikos P. Pitsianis; Gerald George Pechanek; Ricardo Rodriguez
Archive | 2001
Nikos P. Pitsianis; Benjamin Strautin; Sanjay Banerjee; Gerald George Pechanek
Archive | 1999
Gerald George Pechanek; Charles W. Kurak; Larry D. Larsen
Archive | 2004
Gerald George Pechanek; Larry D. Larsen
Archive | 2002
Sergei Yurievich Larin; Gerald George Pechanek; Thomas M. Conte