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Dive into the research topics where Gerald George Pechanek is active.

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Featured researches published by Gerald George Pechanek.


international conference on asic | 2002

Any-size instruction abbreviation technique for embedded DSPs

Gerald George Pechanek; Sergei Y. Larin; Thomas M. Conte

There exist a whole class of systems, which presents critical requirements for code density, efficient memory usage, low power and performance. A representative of this class are embedded DSP systems for SOC. This work presents a method for entropy-bounded encoding of an original ISA and decoupling it from a DSP core. The encoding allows the instruction storage to be used with high efficiency, which is only bounded by the information contents of an application, and relaxes any restrictions imposed on the ISA by the physical memory and branching mechanism. The concept is illustrated with an exemplary commercial DSP processor showing a reduction of the required instruction memory space of greater than 40% without significant impact on the instruction fetch stage of the DSP pipeline.


Archive | 2003

Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution

Thomas L. Drabenstott; Gerald George Pechanek; Edwin Franklin Barry; Charles W. Kurak


Archive | 1998

Manifold array processor

Gerald George Pechanek; Charles W. Kurak


Archive | 2001

Methods and apparatus for scalable array processor interrupt detection and response

Edwin Franklin Barry; Patrick R. Marchand; Gerald George Pechanek; Larry D. Larsen


Archive | 2005

Methods and apparatus for power control in a scalable array of processor elements

Patrick R. Marchand; Gerald George Pechanek; Edward A. Wolff


Archive | 1999

Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray Architecture

Nikos P. Pitsianis; Gerald George Pechanek; Ricardo Rodriguez


Archive | 2001

Methods and apparatus for indirect VLIW memory allocation

Nikos P. Pitsianis; Benjamin Strautin; Sanjay Banerjee; Gerald George Pechanek


Archive | 1999

Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture

Gerald George Pechanek; Charles W. Kurak; Larry D. Larsen


Archive | 2004

Methods and apparatus for transforming, loading, and executing super-set instructions

Gerald George Pechanek; Larry D. Larsen


Archive | 2002

Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture

Sergei Yurievich Larin; Gerald George Pechanek; Thomas M. Conte

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