Larry D. Larsen

Methods and apparatus for scalable instruction set architecture with dynamic compact instructions

Methods and apparatus for scalable array processor interrupt detection and response

Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register file

Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture

Methods and apparatus for transforming, loading, and executing super-set instructions

Providing parallel operand functions using register file and extra path storage

Methods and apparatus for data dependent address operations and efficient variable length code decoding in a vliw processor

Procedes et dispositif de reaction et de detection d'interruption d'un processeur dans un groupement echelonnable

Methods and apparatus for abbreviated instruction and configurable processor architecture

Verfahren und vorrichtungen für eine skalierbare befehlsmengenarchitektur mit dynamischen kompakten befehlen