Gérald Haller

Effect of physical defect on shmoos in CMOS DSM technologies

Abstract Dynamic laser stimulation (DLS) techniques based on operating integrated circuits (ICs) become a standard failure analysis technique for soft defect localization. This type of defect is getting more and more common with advanced technology; therefore, DLS is becoming a key technique for defect localization. To perform this technique, the determination of a pass–fail border in shmoo plot is necessary. It is essential to know the impact of the defect on the shmoo plot shape with different defects. This paper presents shmoos plots simulation for common defects encountered in ICs failure analysis. Ability of DLS to detect defects according to their resistances and capacitances values are clearly established. In the second part of this paper, case studies which validate simulations results are presented.

Characterization and TCAD simulation of 90 nm technology transistors under continous photoelectric laser stimulation for failure analysis improvement

This study is driven by the need to optimize failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. It is therefore mandatory to understand the behavior of elementary devices to laser illumination, in order to model and predict the behavior of more complex circuits. This paper characterizes and analyses photoelectric effects induced by static 1064 nm wavelength laser on a 90 nm technology NMOS transistor. Comparisons between photocurrents in short or long channel transistor, or in function of its state (on or off) are presented. Experimental measurements are correlated to Finite Elements Modeling Technology Computer Aided Design (TCAD) analyses, which gives a physical insight of carriers generation and transport in the devices.

Effects of 1064 nm laser on MOS capacitor

This study is driven by the need to improve failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. Thus, it is mandatory to understand the behavior of elementary devices under laser illumination, in order to model and predict the behavior of more complex circuits. This paper characterizes and analyses effects induced by static photoelectric laser stimulation (1064 nm) on a 90 nm technology metal-oxide-semiconductor (MOS) capacitor. On n-MOS capacitor the laser induces interface traps in the low part of the silicon band-gap, contrary to p-MOS capacitor where it is in the upper half part of the gap. It is also shown that electric stress increases the density of such interface traps.

Photoelectric Laser Stimulation applied to Latch-Up phenomenon and localization of parasitic transistors in an industrial failure analysis laboratory

This paper describes a new technique that uses a 1064 nm wavelength laser for failure analysis of CMOS integrated circuits. We propose a new flow to deal with Latch-Up (LU) phenomenon issues and for this we have developed a new technique that allows localizing areas sources of Latch-Up triggering in an Integrated Circuit (IC). An effectiveness of this method is verified by an experiment on a microcontroller and has proved to be useful for finding the sensitive location. The proposed methodology further extends the capabilities of Photoelectric Laser Stimulation (PLS) in qualification and characterization domains.

Evaluation of scanning capacitance microscopy sample preparation by focused ion beam

Due to the continuous reduction of the critical dimensions of semiconductor devices, it becomes very important to know the two dimensional (2D) doping profile for electrical performance of devices. Scanning Capacitance Microscopy (SCM) is a powerful technique for qualitative analysis of 2D doping species distribution, measuring small capacitance variations with high spatial resolution. For 2D carrier profiling, the region of interest must be accessible to the profiling instrument. SCM samples require cross-sectioning to expose the inner sample at a visible surface. In some analysis, the failure is localized at a very accurate address up to hundreds of nanometers. With the traditional polishing method of sample preparation it is very difficult to reach the exact location. For this reason we are investigating a new way to prepare SCM sample with Focused Ion Beam (FIB) and plasma etch in order to accurately choose the scanning zone. This paper presents a method to obtain SCM scans after a sample preparation by FIB and the influence of the FIB and the Plasma etcher on cross-sectioned SCM samples.

Implementing Thermal Laser and Photoelectric Laser Stimulation in a failure analysis laboratory

First Photoelectric Laser Stimulation results (OBIC or LIVA) obtained with an upgraded version of a PHEMOS 1000 from Hamamatsu are presented. This technique is applied in a case study concerning ESD defect localization and is compared to the Thermal Laser Stimulation one.

Improving defect localization techniques with laser beam with specific analysis and set-up modules

This paper describes a way to improve commonly used static laser stimulation techniques. Several analysis and set-up modules are presented to enrich them. Quickly assembled, combinable and easily adaptable, they allow for example to face atypical failure analysis cases. Effectiveness of this methodology is verified by two cases study. The proposed methodology further extends the capabilities of Laser Stimulation techniques in debug design and characterization domains.

Scan-based ATPG diagnostic and optical techniques combination: A new approach to improve accuracy of defect isolation in functional logic failure

Nowadays, with the increasing complexity of new VLSI circuits, laser stimulation or emission techniques and scan-based ATPG diagnostic reach their limits in functional logic failure. To overcome these limitations, a new methodology has been established. This methodology, presented in this paper, combines the advantages of both approaches in order to improve accuracy of fault isolation and defect localization.

Impact of semiconductors material on IR Laser Stimulation signal

Abstract In failure analysis laboratory, infrared laser stimulation techniques are more and more used for performing accurate defect localization on IC surface. Signatures obtained on metallic elements are well known, but weak data are available on signatures of semiconductors elements. Our investigations consist of studying impact of semiconductors materials on IR Laser Stimulation signal during a failure analysis. Frontside and backside Thermal Laser Stimulation (TLS) experiments were performed on n+/p+ diffusion and polycrystalline resistors from 0.18μm technology, both silicided (CoSi2) and unsilicided. Experimental results are presented and discussed for different W/L ratios. The impact of different semiconductors materials on TLS measurements is discussed and verified by experiment.

Thermal laser stimulation effects on NMOS transistor

Thermal laser stimulation techniques allow localizing defects on integrated circuits from front side and backside. Sometimes, the understanding of signatures given by these mapping techniques appears difficult. Their interpretations are often referenced from simple structures such as metal lines. Understanding of TLS signatures on elementary MOS transistors, seems to be necessary. This study is based on thermal laser effects on a NMOS transistor operated in the saturation regime. The drain current variation upon laser heating is reported. Experimental results obtained on the PHEMOS 1000 system from Hamamatsu are presented.