V. Goubier

Effect of physical defect on shmoos in CMOS DSM technologies

Abstract Dynamic laser stimulation (DLS) techniques based on operating integrated circuits (ICs) become a standard failure analysis technique for soft defect localization. This type of defect is getting more and more common with advanced technology; therefore, DLS is becoming a key technique for defect localization. To perform this technique, the determination of a pass–fail border in shmoo plot is necessary. It is essential to know the impact of the defect on the shmoo plot shape with different defects. This paper presents shmoos plots simulation for common defects encountered in ICs failure analysis. Ability of DLS to detect defects according to their resistances and capacitances values are clearly established. In the second part of this paper, case studies which validate simulations results are presented.

Characterization and TCAD simulation of 90 nm technology transistors under continous photoelectric laser stimulation for failure analysis improvement

This study is driven by the need to optimize failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. It is therefore mandatory to understand the behavior of elementary devices to laser illumination, in order to model and predict the behavior of more complex circuits. This paper characterizes and analyses photoelectric effects induced by static 1064 nm wavelength laser on a 90 nm technology NMOS transistor. Comparisons between photocurrents in short or long channel transistor, or in function of its state (on or off) are presented. Experimental measurements are correlated to Finite Elements Modeling Technology Computer Aided Design (TCAD) analyses, which gives a physical insight of carriers generation and transport in the devices.

Effects of 1064 nm laser on MOS capacitor

This study is driven by the need to improve failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. Thus, it is mandatory to understand the behavior of elementary devices under laser illumination, in order to model and predict the behavior of more complex circuits. This paper characterizes and analyses effects induced by static photoelectric laser stimulation (1064 nm) on a 90 nm technology metal-oxide-semiconductor (MOS) capacitor. On n-MOS capacitor the laser induces interface traps in the low part of the silicon band-gap, contrary to p-MOS capacitor where it is in the upper half part of the gap. It is also shown that electric stress increases the density of such interface traps.

Photoelectric Laser Stimulation applied to Latch-Up phenomenon and localization of parasitic transistors in an industrial failure analysis laboratory

This paper describes a new technique that uses a 1064 nm wavelength laser for failure analysis of CMOS integrated circuits. We propose a new flow to deal with Latch-Up (LU) phenomenon issues and for this we have developed a new technique that allows localizing areas sources of Latch-Up triggering in an Integrated Circuit (IC). An effectiveness of this method is verified by an experiment on a microcontroller and has proved to be useful for finding the sensitive location. The proposed methodology further extends the capabilities of Photoelectric Laser Stimulation (PLS) in qualification and characterization domains.

Electro Optical Terahertz Pulse Reflectometry, a non destructive technique to localize defects on various type of package

Abstract Localizing defects (particularly, dead open and resistive open defects) at package level is becoming a critical challenge for Failure Analysis Laboratories due to package miniaturisation and increased complexity. One of the well-known approaches to address this set of problems within a Device Under Test (DUT) is Time Domain Reflectometry (TDR). The main limitation of this technique is the lack of distance-to-defect accuracy and sensitivity. Electro Optical Terahertz Pulse Reflectometry (EOTPR) overcomes these limitations by using photoconductive terahertz generation and detection technology, resulting in a system with: (i) high measurement bandwidth, (ii) extremely low time base jitter, and (iii) high time base accuracy and range with greater sensitivity. In this paper we present case studies in which EOTPR has been successfully applied to a series of different device types.

Improving defect localization techniques with laser beam with specific analysis and set-up modules

This paper describes a way to improve commonly used static laser stimulation techniques. Several analysis and set-up modules are presented to enrich them. Quickly assembled, combinable and easily adaptable, they allow for example to face atypical failure analysis cases. Effectiveness of this methodology is verified by two cases study. The proposed methodology further extends the capabilities of Laser Stimulation techniques in debug design and characterization domains.

Scan-based ATPG diagnostic and optical techniques combination: A new approach to improve accuracy of defect isolation in functional logic failure

Nowadays, with the increasing complexity of new VLSI circuits, laser stimulation or emission techniques and scan-based ATPG diagnostic reach their limits in functional logic failure. To overcome these limitations, a new methodology has been established. This methodology, presented in this paper, combines the advantages of both approaches in order to improve accuracy of fault isolation and defect localization.

Best test pattern failure analysis flow for functional logic failure localization by IR-OBIRCH technique

The optical IR-OBIRCh technique is a standard failure analysis tool used to localize defects that are located at interconnects layers levels. For a functional logic failure, a failing test pattern is used to condition the device into a particular logic state to generate the failure. Commonly, the defect is detected for a set of test patterns. All test patterns will not provide the same IR-OBIRCh response. A random selection of test patterns may not lead to localize the defect by IR-OBIRCh technique or give fake results. We have performed an extended study of IR-OBIRCh response of a functional logic failure in function of test patterns. Based on these results a best test pattern failure analysis flow has been developed and implemented in order to localize a functional logic failure with IR-OBIRCh technique.

Generic simulator for faulty IC.

Soft defect impact on electrical characteristics is becoming a key issue for device analysis after reliability test as well as for products coming back from the field. Simulating the effect of defects plays a key role. Unfortunately, the complexity of the devices induces a long simulation time, while technology information is not always available at end user side, especially regarding very deep submicron CMOS technology. Having a fast and efficient generic simulator is of great interest for reliability test. In this paper, by comparing the design kit model from ST Microelectronics to the BSIM4 compact model on Microwind3.0, we will show the possibility to run fast simulations with a generic simulation tool. The final application of this generic simulator is to obtain the dynamic behavior in light emission on the failed structures.

Optimization of picosecond laser processing for microscopy sample preparation prior to Ion milling polishing

Microchips are more and more complex and designed in thick 3 dimensional packages. In order to access and characterize by electron microscopy (SEM and TEM) any detected defect responsible for malfunction of the device, a large quantity of matter needs to be removed without damaging the surrounded area. The available techniques, such as plasma Focused Ion Beam (FIB), allow achieving high quality surfaces but are limited by their low matter removal rate (∼104 μm3/s). In order to accelerate the process, other techniques such as laser micromachining of the sample prior to FIB polishing are envisioned [1, 2]. In this work, picosecond laser micromachining has been investigated at 3 wavelengths (343, 515 and 1030 nm) in silicon and tested in integrated circuits. In order to minimize the FIB polishing time, the laser induced damaged zone should be the least extended and the micromachined sidewalls should be as vertical and smooth as possible. It is shown that by using sufficiently high fluences and number of pulses, almost vertical and smooth sidewalls can be obtained (see Fig. la) [3]. Moreover, according to the TEM images, sidewalls are only covered by a few hundred nm thick debris layer with limited heat affected zones. These results, coupled with the high matter removal rate (∼106 μm3/s) demonstrate that picosecond laser machining fulfills the requirements for sample preparation. The processing method was successfully tested on microchips as shown by SEM imaging which reveals clean exposed interfaces of underlayers (see Fig. 1b). In addition, using a simple model allowing a better understanding of laser absorption in silicon for picosecond pulses, the conditions (wavelength and fluence) to achieve optimal matter removal rate and ablation efficiency were identified and validated by experimental results.