Gerald Ofner

Embedded wafer level ball grid array (eWLB)

Wafer Level Packaging (fan-in WLB, Wafer Level Ball Grid Array) is the upcoming future packaging technology with many advantages in comparison to standard Ball Grid Array Packages. Advantages are especially the small package dimensions, excellent electrical and thermal performance, highest package interconnect density and integration possibilities at lowest packaging cost. Today, standard (fan-in) WLBs are the technology of choice mainly for small to medium sized chips with a moderate number of interconnects. The reason for the limited number of interconnects is the need to fit all interconnects on the die in a given terminal pitch. Since this is not generally possible, Infineon has developed a fan-out WLB Technology, called embedded Wafer Level Ball Grid Array (eWLB). The technology is based on a reconstituted wafer which is built prior to the thin-film technology, adding space around the dies to increase the possible number of interconnects on the package. This Reconstituted Wafer is afterwards processed by applying dielectric, redistribution, solder stop and balls in a modified thin-film and backend technology. The new wafer level package concept complies with the directives for environmental friendly technologies like WEEE and RoHS. eWLB passed all performed Standard JEDEC reliability tests without optical or electrical fails on a test vehicle basis. We will introduce recent results of the platform development of the eWLB technology and show the capabilities of Infineons molded embedded Wafer Level Package for future system integration.

Embedded wafer level ball grid array (eWLB) technology for system integration

Silicon front-end and assembly and packaging technology more and more merge. In addition interconnect density reaches limits for advanced CMOS technology. In this paper we introduce the fan-out embedded wafer level packaging technology, which is an example to link front-end and packaging technology and offers additional freedom for interconnect design. We demonstrate capabilites for system integration of the eWLB technology, which includes system on chip (SoC) integration and system in package (SiP) integration like side by side and stacking of devices. We highlight the importance of understanding properties of new materials, which influence warpage or heat dissipation. We also show the excellent performance of the eWLB package for mm-wave applications.

System integration with eWLB

Fan-Out Wafer Level Packaging has arrived in the industry. The driving factors for the implementation of this packaging technology are the low packaging and test cost, the excellent electrical and thermal performance, the ability to work with increasing interconnect density on chip side and the potential for Integration of functionality. The increasing demand for new and more advanced electronic products with superior functionality and performance is driving the integration of functionality for future packaging technologies.

Package optimization of a stacked die flip chip based test package

We report a case study for the optimization of a flip chip based stacked die array test package. We demonstrate the importance of package substrate design and substrate thickness on the processibility and package warpage control. We found that for thin substrates copper balancing of the top and bottom die is crucial. We show the impact of flip chip die thickness and substrate thickness on the die attach of the top die(s) in the stack. Investigations on different top die attach alternatives show that tape die attach can have advantages. We demonstrate the importance of the vertical stack structure (i.e. flip chip thickness) and material selection (i.e. mold compound) on the overall warpage control of the package. The results show that even small changes in the package structure can have large impact on the warpage characteristics of the stacked die package

Considerations for a robust moisture performance of a flip chip in package for lead-free soldering

This work provides a comprehensive study on several approaches to obtain a robust lead-free flip chip package. The influence of materials, chip passivation, package configuration and cleaning processes were investigated to provide insights on the effectiveness of each approach to improve the moisture sensitivity level (MSL) performance. Results showed that the underfill/flux compatibility to the chip passivation has a strong influence on the MSL performance. Furthermore, it was observed that the unmolded version generally has a better MSL performance than the molded flip chip in package (FCIP) for a given material combination. However, there is no strong correlation between MSL performance and material properties. The plasma cleaning and defluxing processes were introduced to assess any potential improvement in MSL performance. Based on the results, plasma cleaning was found to be effective in improving the MSL performance. Defluxing evaluation showed potential for MSL performance improvement provided the defluxing process is well controlled. It is also worth noting that with the right underfill/flux/passivation combination, plasma cleaning may not be necessary to achieve the same MSL performance. In summary, this paper has emphasized the importance of mold compound/underfill/flux/passivation compatibility and the effectiveness of an optimized plasma cleaning or defluxing process to improve MSL performance. This study has also sucessfully demonstrated that MSL 1 performance can be achieved with the right choice of materials combination without additional cleaning processes.