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Dive into the research topics where Mary Teo is active.

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Featured researches published by Mary Teo.


electronics packaging technology conference | 2004

Considerations for a robust moisture performance of a flip chip in package for lead-free soldering

Gerald Ofner; Khoon Lam Chua; Mary Teo; Charles Lee

This work provides a comprehensive study on several approaches to obtain a robust lead-free flip chip package. The influence of materials, chip passivation, package configuration and cleaning processes were investigated to provide insights on the effectiveness of each approach to improve the moisture sensitivity level (MSL) performance. Results showed that the underfill/flux compatibility to the chip passivation has a strong influence on the MSL performance. Furthermore, it was observed that the unmolded version generally has a better MSL performance than the molded flip chip in package (FCIP) for a given material combination. However, there is no strong correlation between MSL performance and material properties. The plasma cleaning and defluxing processes were introduced to assess any potential improvement in MSL performance. Based on the results, plasma cleaning was found to be effective in improving the MSL performance. Defluxing evaluation showed potential for MSL performance improvement provided the defluxing process is well controlled. It is also worth noting that with the right underfill/flux/passivation combination, plasma cleaning may not be necessary to achieve the same MSL performance. In summary, this paper has emphasized the importance of mold compound/underfill/flux/passivation compatibility and the effectiveness of an optimized plasma cleaning or defluxing process to improve MSL performance. This study has also sucessfully demonstrated that MSL 1 performance can be achieved with the right choice of materials combination without additional cleaning processes.


international conference on electronic materials and packaging | 2006

FEA Thermal Investigation of Wafer Thinning by Plasma Etching

Foo Lam Wong; Radimin; Mary Teo; Charles Lee

In this work, finite element analysis (FEA) was used to predict transient heating and temperature distribution on the wafer surface during plasma etching process as backgrind (BG) tape degradation after plasma stress relief was observed. The wafer surface temperature during plasma process was measured using temperature indicator strips and used as input temperature for FEA analysis. Parametric studies were performed to analyse the effect of temperature on different Silicon thickness and different wafer contact on electro static chuck (ESC) to understand the temperature distribution during the plasma process. The thermal behaviour of BG tape was also characterised using differential scanning calorimetry (DSC). Perfect wafer contact on ESC predicted 99.1degC after 0.1 s. With presence of air gaps, temperature increases to 105degC and based on DSC analysis, melting is likely to occur. We have demonstrated the application of FEA and DSC methods can be applied to BG tape selection.


international conference on electronic materials and packaging | 2006

Characterization of Fast Cure Anisotropic Conductive and Non-Conductive Adhesives

Mary Teo; Charles Lee

Anisotropic conductive adhesives (ACA) and non-conductive adhesives (NCA) are used in adhesive flip chip technology. An optimized cure process for these ACA and NCA materials is critical to develop the ultimate mechanical and electrical properties of the adhesive flip chip joints. Typically, these adhesives are formulated to achieve complete cure in less than 60 seconds at a cure temperature between 180degC and 250degC. This fast cure characteristic poses great difficulties for conventional cure characterization techniques. In this study, advanced cure monitoring techniques including modulated differential scanning calorimetry (MDSC), dielectric analysis (DEA) and fibre Bragg grating (FBG) were explored. Cure shrinkage was also measured using both FBG and thermomechanical analysis (TMA). Findings showed that MDSC is an improved method for analysis of partial-cured sample compared to conventional DSC. It was also demonstrated that cure characterization for these fast-cure materials is feasible using both DEA and FBG. It is worth noting that both DEA and FBG have potential for in-situ cure monitoring since the sensors can be embedded into the material during actual assembly process. For cure shrinkage measurement, feasibility of FBG was demonstrated in addition to using TMA which has been reported in prior work. Cure shrinkage results obtained using both techniques were found to be in good agreement. In summary, this paper has demonstrated the feasibility of several methodologies for cure behaviour characterization of fast-cure ACA and NCA materials. The key findings from this work represent a significant step towards cure process optimization for the development of reliable adhesive flip chip interconnects.


electronics packaging technology conference | 2006

FEA thermal investigation on plasma etching induced heating during wafer thinning process

Foo Lam Wong; Radimin; Mary Teo; Charles Lee

In this work, finite element analysis (FEA) was used to predict transient heating and temperature distribution on the wafer surface during plasma etching process as backgrind (BG) tape degradation after plasma stress relief was observed. The wafer surface temperature during plasma process was measured using temperature indicator strips and used as input temperature for FEA analysis. A series of parametric studies were performed to analyse the effect of different silicon thickness and different wafer contact on electro static chuck (ESC) to understand the temperature distribution during the plasma process. The thermal behaviour of BG tape was also characterised using differential scanning calorimetry (DSC). Perfect wafer contact on ESC predicted 99.1 degC after 0.1s. With presence of air gaps, temperature increases to 105 degC and based on DSC analysis, melting is likely to occur. Therefore FEA & DSC analysis has demonstrated to be a potential technique for BG tape selection


Archive | 2010

Integrated Circuit Package and a Method for Forming an Integrated Circuit Package

Gerald Ofner; Swain Hong Yeo; Mary Teo; Pei Siang Lim; Khoon Lam Chua


electronics packaging technology conference | 2007

Plasma Surface Modification and Impact on MSL Performance for Flip Chip Packaging

Mary Teo; Ka Yau Lee; Alex Chew; Simon Siak Boon Lim; Charles Lee; Masaru Nonomura


international conference on electronic materials and packaging | 2006

Process and Material Characterization of Die Attach Film (DAF) for Thin Die Applications

Mary Teo; Soh Choew Kheng; Charles Lee


international electronics manufacturing technology symposium | 2006

Assessment of Die Attach Film for Thin Die and SiP Applications

Soh Choew Kheng; Mary Teo; Charles Lee


Archive | 2005

An integrated circuit package and a method for forming an integrated circuit package

Gerald Ofner; Swain Hong Yeo; Mary Teo; Pei Siang Lim; Khoon Lam Chua


Archive | 2006

Semiconductor chip with flip chip contacts, and method for producing semiconductor chip with flip chip contacts

Gerald Ofner; Ai Min Tan; Mary Teo

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Radimin

Infineon Technologies

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