Gerard Baldwin

Wideband 0.18μm CMOS VCO using active inductor with negative resistance

This paper presents a wideband voltage controlled oscillator topology based on an active inductor generating negative resistance. The proposed architecture covers a frequency band between 1.325 GHz - 2.15 GHz with average in-band phase noise of -86 dBc/Hz at 1 MHz offset from the carrier frequency. Power consumption of the oscillator core is 28 mW from a 1.8 V supply. The circuit has been simulated in Eldo RF (Design Architect IC, Mentor Graphics) using UMC 0.18 mum 1P6M Salicide RF CMOS model libraries.

Toward Scalable, Automated Tower-Top Phased Array Calibration

The tower-top deployment of base station electronics could prove of utility in future cellular communication applications. We present a scalable, non-radiative, automated calibration scheme for such a system, which employs an array of independently phased transceivers. By coupling an interlinear row of reference transceivers to the array, feedpoint calibration of the array is possible. The theoretical justification for the scheme is presented together with assessment of the accuracy of calibration possible using commercial off the shelf components.

A Platform for the Development of Software Defined Radio

This paper describes the development of an SDR (software defined radio) platform for use in investigating the requirements for implementing many popular standards such as GSM, WiFi and 3G through SDR. The first stage of this work is to generate specifications for an SDR implementation from various wireless standard requirements. The next stage is the development of suitable reconfigurable hardware. The final stage is the development of suitable software for the reconfiguration of the hardware and the implementation of the standards.

Physical Component Performance Degradation Detection based on Error Probability Analysis

The detection and diagnosis of physical layer faults at system level in communications systems remains problematic. This paper presents a cross layer fault detection scheme, suitable for implementation at higher levels in a communications system, with the ability to detect and diagnose the cause of physical layer failure which results in impaired performance. It is based on the distribution of symbol error frequency and the probability of error of the underlying modulation scheme used in the communications system. With this knowledge, a simple counting algorithm is proposed as a diagnostic tool to implement the methodology.

Performance requirements for analog-to-digital converters in wideband reconfigurable radios

With the current trend towards software defined radio, several candidate architectures for the analog receiver front-end have been presented. A common proposal for software defined reconfigurable radio is to develop a wideband ADC and utilise this for capturing a large segment of the spectrum. This would enable the subsequent signal processing operations of channel selection and data extraction to be carried out by a digital processor. This would allow the radio to be reconfigured by simply changing the software. In analysis of these systems, powerful neighbouring signals, or blockers, are considered but it has been conveniently assumed that suitable dynamic range will be available at the ADC. This is an acceptable assumption in narrowband systems where automatic gain control and analogue channel select filters can be used, but is not appropriate for a wideband system. In this paper we present an analysis based on bit-error-rates (BER) which shows the effect of blockers in a wideband architecture on the performance of the communication link and on the dynamic range requirements of the ADC.

Modeling and design of high-order phase locked loops

In this paper a new stable high order Digital Phase Lock Loop (DPLL) design technique is proposed. PLLs of order greater than two display better noise bandwidth, Bl, than classical second order PLLs. However these are not unconditionally stable as in the second order case. This technique uses linear theory to design the DPLL. The stability of the DPLL is guaranteed by placing a restriction on the system gain. This stability boundary is found by transforming the system transfer function to the Z-domain and plotting the root locus of the LPLL for values of gain where all the system poles lie inside the unit circle. The minimum value of gain where all the poles lie inside the unit circle forms the stability boundary. It is shown that the stability boundary of the LPLL is comparable to the stability boundary of the DPLL. Finally where the above filter design system produces slow lock, gear shifting of the DPLL components is considered. This allows the DPLL to start off with a wide loop bandwidth and switch to the narrow bandwidth once the system has locked.

A modular testbed for hardware reconfigurable radio at the 2.4 GHz ISM band

A modular testbed for use in developing software defined radio is documented in this paper. The testbed is focused on the 2.4 GHz ISM band but may be used at other frequencies. An RF transceiver with variable transmit/receive frequencies and bandwidths is provided. It provides the capability to support many modulation schemes and standards such as GSM, UMTS, IEEE 802.11b and parts of the IEEE802.16 standards. It performs the RF functions of the radio, with the other PHY and MAC layer functions such as equalisation and error-coding being performed by a host computer. It communicates with the host computer system through a USB2 interface allowing data rates of up-to 60Mbytes a second. An API is used for communication with the host computer system allowing for modulation/demodulation and coding/decoding in software on the host system and reconfiguration of the radio system.