Grzegorz Szczepkowski

Wideband 0.18μm CMOS VCO using active inductor with negative resistance

This paper presents a wideband voltage controlled oscillator topology based on an active inductor generating negative resistance. The proposed architecture covers a frequency band between 1.325 GHz - 2.15 GHz with average in-band phase noise of -86 dBc/Hz at 1 MHz offset from the carrier frequency. Power consumption of the oscillator core is 28 mW from a 1.8 V supply. The circuit has been simulated in Eldo RF (Design Architect IC, Mentor Graphics) using UMC 0.18 mum 1P6M Salicide RF CMOS model libraries.

A 90nm, low power VCO with reduced KVCO and sub-band spacing variation

In this paper we present the design of a low power VCO with reduced variations in VCO gain (KVCO) and sub-band spacing resolution (fres). The proposed VCO is designed using a 90nm CMOS process to cover a tuning range of 23%. Variations in KVCO and fres are reduced by factors of 6 and 17 respectively over a conventional sub-banded VCO, designed using the same process, to meet the same tuning range. This makes the proposed VCO more suited to stable PLL operation with its reduced KVCO requirements resulting in an improvement in phase noise performance over the conventional VCO by 2 dB. Due to the reduced loading on the VCO tank achieved by the presented design, power consumption is kept extremely low at 850 μW from a 1 V supply.

Noise and dynamic range of CMOS degenerated active inductor resonators

This paper presents a compensation method of active inductor losses, employing passive gyrator degeneration rather than an external negative impedance converter. Theoretical analysis is confirmed by a comparative simulations of two resonators designed for 434 MHz band, using Eldo RF and Spectre and the UMC 0.18 μm 1P6M process. Presented results show that the proposed loss compensation method achieves comparable noise and large signal performance to a standard active inductor resonator and provides a significant improvement in static power consumption.

Wideband MEMS switched delay lines with high phase linearity

This paper presents a study on different microwave structures used to integrate MEMS devices in printed circuit boards, and their effect on the linear phase response for switched delay lines applications. Three different prototypes were designed to realize the RF tracks required to integrate 0.5 mm pitch MEMS devices together with the meander delay lines. The structures includes: microstrip lines, conventional coplanar waveguides (CPW) and finite grounded coplanar waveguides (FGCPW). The three prototypes were designed to deliver a group delay of 600 ps. Simulations were carried out using CST Microwave Studio. The FGCPW proved to have the highest phase linearity with only ± 4 ps (±0.67%) delay deviations up to 2.7 GHz. The paper also presents the design of two wideband MEMS switched time delay line circuits; one used to provide a fine tuning for the group delay with a step of only 10 ps and another for coarse tuning with 50 ps delay step. Finite grounded coplanar waveguides were selected to obtain a high linearity of phase response. The simulation of the two circuits resulted in a constant delay with relatively small deviations, as well as low insertion and return losses of 0.75 dB and 20 dB, respectively for frequencies up to 5 GHz.

Study of Linearity and Power Consumption Requirements of CMOS Low Noise Amplifiers in Context of LTE Systems and Beyond

This paper presents a study of linearity in wideband CMOS low noise amplifiers (LNA) and its relationship to power consumption in context of Long Term Evolution (LTE) systems and its future developments. Using proposed figure of merit (FoM) to compare 35 state-of-the-art LNA circuits published over the last decade, the paper explores a dependence between amplifier performance (i.e., combined linearity, noise figure, and gain) and power consumption. In order to satisfy stringent linearity specifications for LTE standard (and its likely successors), the paper predicts that LNA FoM increase in the range of

Open loop approach to design low voltage, 400 mV, 1.3 mW, 10 GHz CMOS class-B VCO

The paper presents a method for design of LC cross-coupled oscillators based on an open loop technique and its practical application leading to a high frequency CMOS oscillator prototype. Thanks to the proposed approach, the main circuit parameters such as loaded quality factor (responsible for phase noise performance of LC oscillator) and steady-state oscillation amplitude, can be extracted without the necessity of time consuming transient simulations. The presented method is not technology specific and allows fast calculations under changing bias conditions. The proposed 130 nm CMOS prototype operates at 10 GHz from a 400mV power supply achieving an average SSB phase noise of -110 dBc/Hz at 1 MHz offset from the carrier and a fractional bandwidth of more than 7.5%. Low average power consumption of 1.3 mW RMS, has been obtained by biasing the oscillator devices to operate in class-B i.e. VGS = VDD = Vth.