Gerhard Lienhart

Using floating-point arithmetic on FPGAs to accelerate scientific N-Body simulations

This paper investigates the usage of floating-point arithmetic on FPGAs for N-Body simulation in natural science. The common aspect of these applications is the simple computing structure where forces between a particle and its surrounding particles are summed up. The role of reduced precision arithmetic is discussed, and our implementation of a floating-point arithmetic library with parameterized operators is presented. On the base of this library, implementation strategies of complex arithmetic units are discussed. Finally the realization of a fully pipelined pressure force calculation unit consisting of 60 floating-point operators with a resulting performance of 3.9 Gflops on an off the shelf FPGA is presented.

From Newton to Einstein – N-body dynamics in galactic nuclei and SPH using new special hardware and astrogrid-D

The dynamics of galactic nuclei containing multiple supermassive black holes is modelled including relativistic dynamics. It is shown that for certain initial conditions there is no stalling problem for the relativistic coalescence of supermassive black hole binaries. This astrophysical application and another one using a smoothed particle hydrodynamics code are our first use cases on a new computer architecture using GRAPE and new MPRACE accelerator cards based on reconfigurable chips, developed in the GRACE project. We briefly discuss our science applications and first benchmarks obtained with the new hardware. Our present architecture still relies on the GRAPE special purpose hardware (not reconfigurable), but next generations will focus on new architectural approaches including custom network and computing architectures. The new hardware is embedded into national and international grid infrastructures.

An FPGA-based video compressor for H.263 compatible bit streams

This paper presents an architecture for video encoding according to the H.263 standard for video conference systems. The implementation is based on an commercial available FPGA and is embedded in a PCI plug-in card with on-board SRAM plus external SRAM. The most complex part of the H.263 protocol, a base-line encoder, could already be implemented and is able to operate at 30 MHz. This leads to a maximum compression speed of 120 Mbit/s allowing simultaneous real-time procession of several video streams in a single reconfigurable chip. Soon the progress of FPGA integration density will make it possible to implement coding options, too. The use of FPGA technology enables adapting the hardware to various protocols and environments by software and therefore to save development time and hardware costs.

An FPGA-based video compressor for H.263 compatible bitstreams

This paper presents an architecture for video encoding according to the H.263 standard for video conference systems. The implementation is based on an commercial available FPGA and is embedded in a PCI plug-in card with on-board SRAM plus external SRAM. The most complex part of the H.263 protocol, a base-line encoder, could already be implemented and is able to operate at 30 MHz. This leads to a maximum compression speed of 120 Mbit/s allowing simultaneous real-time procession of several video streams in a single reconfigurable chip. Soon the progress of FPGA integration density will make it possible to implement coding options, too. The use of FPGA technology enables adapting the hardware to various protocols and environments by software and therefore to save development time and hardware costs.

Rapid development of high performance floating-point pipelines for scientific simulation

In the last years, FPGAs became capable of performing complex floating-point based calculations. For many applications, highly parallel calculation units can be implemented which deliver a better performance than general-purpose processors. This paper focuses on applications where the calculations can be done in a pipeline, as it is often the case for simulations. A framework for rapid design of such calculation pipelines is described. The central part is a Perl based code generator, which automatically assembles floating-point operators into synthesizable hardware description code where the generator is directed by a pipeline description file. The framework is supplemented by various floating-point operators and support modules, which allow generating ready-to-use pipelines. The code generator dramatically reduces development time and produces high-quality results. The performance of the framework is demonstrated by the implementation of pipelines for gravitational forces and hydrodynamics

On Buffer Management Strategies for High Performance Computing with Reconfigurable Hardware

Different buffering strategies for communicating between custom computing machines and host computers are presented and compared. An approach that allows for the integration of diverse buffering schemes with arbitrary data conversion is presented and provides between 23% and 82% improvement when compared with separate operations.

Rapid Design of Special-Purpose Pipeline Processors with FPGAs and its Application to Computational Fluid Dynamics

This paper presents a framework for rapid development of FPGA based custom processors based on floating-point calculation units. The framework consists of a fully parameterized floating-point library, an easy-to-use pipeline generator and an interface generator for memory and I/O-modules. The performance of this approach is shown for the implementation of an SPH-algorithm.