Gernot Koch

A prototyping environment for hardware/software codesign in the COBRA project

We present a prototyping environment with special benefit for hardware/software codesign which we use as target architecture in the COBRA project. This architecture is very flexible, easy extensible, and provides a high gate complexity. It supports standard processor integration as well as processor emulation.<<ETX>>

Breakpoints and breakpoint detection in source-level emulation

In this paper we discuss, what breakpoints in Source Level Emulation are, how we can work with them and how we have to change the cicuit generated by high level synthesis to do so. We show the details of breakpoint encoding and detection in our approach. The presented approach allows for breakpoint detection by hardware means without seriously slowing down the circuit or dramatically increasing its size.

Debugging of behavioral VHDL specifications by source level emulation

We present an approach to accelerate the validation speed of behavioral VHDL system specifications through the use of hardware emulation. The method allows source level debugging of behavioral, algorithmic VHDL in a way similar to source level debugging known from software programming languages. We can set breakpoints in the source code and evaluate the contents of variables by reading the registers of the circuit when a breakpoint is reached.

Exploiting FPGA-features during the emulation of a fast reactive embedded system

This paper presents the emulation of an embedded system with hard real time constraints and response times of about 220μs. We show that for such fast reactive systems, the software overhead of a Real Time Operating System (RTOS) becomes a limiting factor, consuming up to 77% of the total execution performance. We analyze features of different FPGA architectures in order to solve the system performance bottleneck. We show that moving functionality from software to hardware through exploiting the fine grained on-chip SRAM capability of the Xilinx XC4000 architecture, that feature eliminates the RTOS overhead by only a slight increase of about 28% of the used FPGA CLB resources. These investigations have been conducted using our own emulation environment called SPYDER-CORE-P1.

Behavioral emulation of synthesized RT-level descriptions using VLIW architectures

Describes techniques that allow VLIW architectures to be used for the behavioral emulation of RT-level descriptions. The starting point of the techniques is a behavioral description at the algorithmic level, e.g. VHDL. This description is transformed into RT-level descriptions of the datapath and controller. The controller is given as a finite state machine. We show how to map these descriptions onto assembly code that can be executed on a VLIW microprocessor. We found the Texas Instruments TMS320C6x series of DSP chips to be suitable candidates for the mapping.

Co-emulation and debugging of HW/SW-systems

Presents a method that allows one to observe and control the emulation of communicating systems consisting of hardware (HW) and software (SW) parts. The approach provides the ability to set breakpoints in either technology, without breaking the protocol or losing data. Systems may contain several SW and HW processes. Each process runs in a separate debugger, while the presented approach provides the necessary synchronization between the processes to preclude loss of data at the communication interfaces due to breakpoints. Therefore it allows the operation to continue after a breakpoint, which is essential for interactive debugging.

System prototyping in the COBRA project

Abstract This paper summarizes the workplan of the COBRA project. Thereby it emphasizes the work concerning our prototyping environment with special benefit for hardware/software codesign which we use as target architecture in COBRA. This architecture is very flexible, easily extensible, and provides a high gate capacity. It supports standard processor integration as well as processor emulation.

Breakpoints and breakpoint detection in source level emulation

In this paper we discuss, what breakpoints in source level emulation are, how we can work with them and how we have to change in the circuit generated by high level synthesis to do so. We show the details of breakpoint encoding and detection in our approach. The presented approach allows for breakpoint detection by hardware means without seriously slowing down the circuit or dramatically increasing its size.

Hardware-Software Prototyping from LOTOS

In this paper we present an extension to the co-design approach based on LOTOS presented in Fourth International Workshop on Hardware-Software Co-Design, 1996. In this new version we add a prototyping stage to our design flow, that allows to validate the design at the implementation level. We present the complete approach, stressing the prototyping stage after partitioning. An example of an Ethernet bridge serves us to illustrate our approach and present some results.

System validation by source level emulation of behavioral VHDL specifications

We present an approach to accelerate the validation speed of behavioral VHDL system specifications through the use of hardware emulation. The method allows source level debugging of behavioral, algorithmic VHDL in a way similar to source level debugging known from software programming languages. We can set breakpoints in the source code and evaluate the contents of variables by reading the registers of the circuit when a breakpoint is reached.