U. Kebschull

Multilevel logic synthesis based on functional decision diagrams

The authors introduce an efficient data structure for Boolean function representation and present a new algorithm for the synthesis of multilevel logic. Other algorithms represent Boolean functions in the operational domain using Sum-of-Products representations. The authors prefer the synthesis in the functional domain using the less complex Reed-Muller Expansion. The algorithm bases on a new efficient representation, the so-called functional decision diagrams, which are herewith presented. The authors implemented this algorithm, the results are encouraging.<<ETX>>

A prototyping environment for hardware/software codesign in the COBRA project

We present a prototyping environment with special benefit for hardware/software codesign which we use as target architecture in the COBRA project. This architecture is very flexible, easy extensible, and provides a high gate complexity. It supports standard processor integration as well as processor emulation.<<ETX>>

Efficient graph-based computation and manipulation of functional decision diagrams

An efficient canonical representation for arbitrary Boolean functions, the functional decision diagrams (FDDs), are presented. FDDs are a graphical representation of the Reed-Muller coefficients as BDDs are a representation of the function table. Some algorithms to manipulate FDDs and generate a functional decision diagram from a BDD are presented. The results are very encouraging and show that FDDs are applicable for new approaches to Reed-Muller logic synthesis.<<ETX>>

Description and simulation of hardware/software systems with Java

The specification language is a critical component of the hardware-software co-design process since it is used for functional validation and as a starting point for hardware- software partitioning and co-synthesis. This paper pro poses the Java programming language as a specification language for hardware-software systems. Java has several characteristics that make it suitable for system specification. However, static control and dataflow analysis of Java programs is problematic because Java classes are dynamically linked. This paper provides a general solution to the problem of statically analyzing Java programs using a technique that pre-allocates most class instances and aggressively resolve memory aliasing using global analysis. The output of our analysis is a control dataflow graph for the input specification. Our results for sample designs show that the analysis can extract fine to coarse-grained concurrency for subsequent hardware-software partitioning and co-synthesis steps of the hardware-software co- design process to exploit.In this paper a newly developed object model is presented which allows the description of hardware/software systems in all its parts. An adaption of the component model, JavaBeans, allows to combine different kinds of reuse in one unitary language. A model based design flow and some tools are presented and applied to a JPEG example.

Breakpoints and breakpoint detection in source-level emulation

In this paper we discuss, what breakpoints in Source Level Emulation are, how we can work with them and how we have to change the cicuit generated by high level synthesis to do so. We show the details of breakpoint encoding and detection in our approach. The presented approach allows for breakpoint detection by hardware means without seriously slowing down the circuit or dramatically increasing its size.

FPGA implementation of a 32x32 autocorrelator array for analysis of fast image series

With the evolving technology in CMOS integration, new classes of 2D-imaging detectors have recently become available. In particular, single photon avalanche diode (SPAD) arrays allow detection of single photons at high acquisition rates (≥ 100 kfps), which is about two orders of magnitude higher than with currently available cameras. Here we demonstrate the use of a SPAD array for imaging fluorescence correlation spectroscopy (imFCS), a tool to create 2D maps of the dynamics of fluorescent molecules inside living cells. Time-dependent fluorescence fluctuations, due to fluorophores entering and leaving the observed pixels, are evaluated by means of autocorrelation analysis. The multi-τ correlation algorithm is an appropriate choice, as it does not rely on the full data set to be held in memory. Thus, this algorithm can be efficiently implemented in custom logic. We describe a new implementation for massively parallel multi-τ correlation hardware. Our current implementation can calculate 1024 correlation functions at a resolution of 10 μs in real-time and therefore correlate real-time image streams from high speed single photon cameras with thousands of pixels.

ALICE HLT High Speed Tracking on GPU

The on-line event reconstruction in ALICE is performed by the High Level Trigger, which should process up to 2000 events per second in proton-proton collisions and up to 300 central events per second in heavy-ion collisions, corresponding to an input data stream of 30 GB/s. In order to fulfill the time requirements, a fast on-line tracker has been developed. The algorithm combines a Cellular Automaton method being used for a fast pattern recognition and the Kalman Filter method for fitting of found trajectories and for the final track selection. The tracker was adapted to run on Graphics Processing Units (GPU) using the NVIDIA Compute Unified Device Architecture (CUDA) framework. The implementation of the algorithm had to be adjusted at many points to allow for an efficient usage of the graphics cards. In particular, achieving a good overall workload for many processor cores, efficient transfer to and from the GPU, as well as optimized utilization of the different memories the GPU offers turned out to be critical. To cope with these problems a dynamic scheduler was introduced, which redistributes the workload among the processor cores. Additionally a pipeline was implemented so that the tracking on the GPU, the initialization and the output processed by the CPU, as well as the DMA transfer can overlap. The GPU tracking algorithm significantly outperforms the CPU version for large events while it entirely maintains its efficiency.

Accelerating Image Analysis for Localization Microscopy with FPGAs

Localization microscopy enhances the resolution of fluorescence light microscopy by about an order of magnitude. Single fluorescent molecules act as switchable markers. Their detected signals can be fitted with a two-dimensional Gaussian distribution and thus located with sub-pixel resolution. In this paper we propose that these fits can be done by calculating the center of mass instead of an iterative least-square fit without loosing precision. The simplification of the algorithm leads to an acceleration of more than a factor of 100 and enables an FPGA implementation with an additional performance boost by a factor of 225. Our findings allow the real-time processing of current and future image data rates in localization microscopy.

Debugging of behavioral VHDL specifications by source level emulation

We present an approach to accelerate the validation speed of behavioral VHDL system specifications through the use of hardware emulation. The method allows source level debugging of behavioral, algorithmic VHDL in a way similar to source level debugging known from software programming languages. We can set breakpoints in the source code and evaluate the contents of variables by reading the registers of the circuit when a breakpoint is reached.

Behavioral emulation of synthesized RT-level descriptions using VLIW architectures

Describes techniques that allow VLIW architectures to be used for the behavioral emulation of RT-level descriptions. The starting point of the techniques is a behavioral description at the algorithmic level, e.g. VHDL. This description is transformed into RT-level descriptions of the datapath and controller. The controller is given as a finite state machine. We show how to map these descriptions onto assembly code that can be executed on a VLIW microprocessor. We found the Texas Instruments TMS320C6x series of DSP chips to be suitable candidates for the mapping.