Ghiath Al-Kadi

A Hardware Task Scheduler for Embedded Video Processing

Modern embedded Systems-on-a-Chip deploy multiple programmable cores to meet increasing performance requirements of video, graphics, and modem applications. However, software implementations of task scheduling and inter-task synchronization often limit performance improvements of multicores. Remarkably, several demanding video applications (e.g. H.264 video decoding) rely on task dependency graphs that can be constructed from a simple dependency pattern. Based on such a pattern, our novel hardware task scheduler can quickly create, order, synchronize and map tasks to cores. We found that our hardware task scheduler speeds up a Quad HD H.264 video decoding by 1.17 times compared to a chip multi-processor with a state-of-the-art hardware task queues. Moreover, our hardware task scheduler allows decreasing the number of cores needed to meet the real-time performance requirements for the H.264 decoder and, consequently, reduces the silicon area of the multicore by up to 12.5%.

A 13.56 Mbps PSK receiver for very high data rate 13.56MHz smart card and NFC applications

In order to increase the data rate of 13.56MHz inductively coupled systems, such as contactless smartcards, e-Passports and near field communication devices (NFC) devices, a multi-level Phase Shift Keying (PSK) modulation was proposed to the ISO standardization body. The challenge of increasing the data rate within the same power budget led to the design of a low-power analog/mixed signal 16PSK demodulator, as well as a digital signal processing hardware IP that estimates and equalizes the channel. The total measured current consumption of the analog front end in 140nm CMOS is less than 100μA, with an area of 0.07mm2. The digital IP current and area estimation in 140nm CMOS are respectively 750μA and 0.24mm2. The evaluated system demonstrates a bit error rate (BER) of 10-6 for data rates up to 10.17 Mbps and a BER of 10-5 for 13.56 Mbps. A Hamming coding scheme is utilized to achieve frame error rates below 2%.

A 13.56Mbps PSK receiver for 13.56MHz RFID applications

This paper presents a receive chain for very-high bit rate (VHBR) communication over a short range 13.56MHz inductively coupled interface, using multi-bit-per-symbol phase-shift keying (PSK) as proposed for the ISO14443 VHBR amendment. A data rate of up to 13.56Mbps is achieved. The receiver consists of an analog front-end IC followed by an FPGA-based digital baseband processor (DSP). The analog front-end IC recovers the carrier from the antenna signal and performs PSK demodulation using an 8-bit time-to-digital converter (TDC). It consumes 100μA in the 13.56Mbps data rate mode. The FPGA-based DSPs main functions are symbol clock recovery in a closed-loop with the analog front-end as well as adaptive equalization. Target bit error rates of below 2·10-4 were achieved for transmitted field strengths above 1.2A/m.

Meandering based parallel 3DRS algorithm for the multicore era

This paper presents a method to parallelize the meandering based 3D recursive search (3DRS) motion estimation algorithm used in scan-rate up-conversion. The proposed algorithm is scalable and can easily be mapped to multiple processing units such as multithreaded processors, multicores and/or co-processors in order to cope up with the increasingly hard to meet real time requirements of next generation video devices. Experiments show that the picture quality of the proposed parallel 3DRS algorithm is as good as the original non-parallelized algorithm for most video sequences.

Balancing Programmability and Silicon Efficiency of Heterogeneous Multicore Architectures

Multicore architectures provide scalable performance with a lower hardware design effort than single core processors. Our article presents a design methodology and an embedded multicore architecture, focusing on reducing the software design complexity and boosting the performance density. First, we analyze characteristics of the Task-Level Parallelism in modern multimedia workloads. These characteristics are used to formulate requirements for the programming model. Then we translate the programming model requirements to an architecture specification, including a novel low-complexity implementation of cache coherence and a hardware synchronization unit. Our evaluation demonstrates that the novel coherence mechanism substantially simplifies hardware design, while reducing the performance by less than 18% relative to a complex snooping technique. Compared to a single processor core, the multicores have already proven to be more area- and energy-efficient. However, the multicore architectures in embedded systems still compete with highly efficient function-specific hardware accelerators. In this article we identify five architectural methods to boost performance density of multicores; microarchitectural downscaling, asymmetric multicore architectures, multithreading, generic accelerators, and conjoining. Then, we present a novel methodology to explore multicore design spaces, including the architectural methods improving the performance density. The methodology is based on a complex formula computing performances of heterogeneous multicore systems. Using this design space exploration methodology for HD and QuadHD H.264 video decoding, we estimate that the required areas of multicores in CMOS 45 nm are 2.5 mm2 and 8.6 mm2, respectively. These results suggest that heterogeneous multicores are cost-effective for embedded applications and can provide a good programmability support.

Rapid Technology-Aware Design Space Exploration for Embedded Heterogeneous Multiprocessors

Multicore architectures provide scalable performance with a hardware design effort lower than for a single core processor with similar performance. This chapter presents a design methodology and an embedded multicore architecture focusing on boosting performance density and reducing the software design complexity. The methodology is based on a predictive formula computing performance of heterogeneous multicores, which allows drastic pruning of the design space for few accurate simulations. Using this design space exploration methodology for high definition and quad high definition H.264 video decoding, the resulting areas for a multicore system in CMOS 45 nm are 2.5 and 8.6 mm2, respectively. These results show that heterogeneous chip multiprocessors are cost-effective for embedded applications.