Massimo Ciacci

A 13.56 Mbps PSK receiver for very high data rate 13.56MHz smart card and NFC applications

In order to increase the data rate of 13.56MHz inductively coupled systems, such as contactless smartcards, e-Passports and near field communication devices (NFC) devices, a multi-level Phase Shift Keying (PSK) modulation was proposed to the ISO standardization body. The challenge of increasing the data rate within the same power budget led to the design of a low-power analog/mixed signal 16PSK demodulator, as well as a digital signal processing hardware IP that estimates and equalizes the channel. The total measured current consumption of the analog front end in 140nm CMOS is less than 100μA, with an area of 0.07mm2. The digital IP current and area estimation in 140nm CMOS are respectively 750μA and 0.24mm2. The evaluated system demonstrates a bit error rate (BER) of 10-6 for data rates up to 10.17 Mbps and a BER of 10-5 for 13.56 Mbps. A Hamming coding scheme is utilized to achieve frame error rates below 2%.

A 13.56Mbps PSK receiver for 13.56MHz RFID applications

This paper presents a receive chain for very-high bit rate (VHBR) communication over a short range 13.56MHz inductively coupled interface, using multi-bit-per-symbol phase-shift keying (PSK) as proposed for the ISO14443 VHBR amendment. A data rate of up to 13.56Mbps is achieved. The receiver consists of an analog front-end IC followed by an FPGA-based digital baseband processor (DSP). The analog front-end IC recovers the carrier from the antenna signal and performs PSK demodulation using an 8-bit time-to-digital converter (TDC). It consumes 100μA in the 13.56Mbps data rate mode. The FPGA-based DSPs main functions are symbol clock recovery in a closed-loop with the analog front-end as well as adaptive equalization. Target bit error rates of below 2·10-4 were achieved for transmitted field strengths above 1.2A/m.