Gi-Ho Park

A selective filter-bank TLB system

We present a selective filter-bank translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks with a small two-bank buffer, called as a filter-bank buffer, located above its associated bank. Either a filter-bank buffer or a main bank TLB can be selectively accessed based on two bits in the filter-bank buffer. Energy savings are achieved by reducing the number of entries accessed at a time, by using filtering and bank mechanism. The overhead of the proposed TLB turns out to be negligible compared with other hierarchical structures. Simulation results show that the Energy*Delay product can be reduced by about 88% compared with a fully associative TLB, 75% with respect to a filter-TLB, and 51% relative to a banked-filter TLB.

Reconfigurable Address Collector and Flying Cache Simulator

Trace-driven simulation is widely used to evaluate the cache memory system. The accuracy of the trace-driven simulation depends on the accuracy and length of the trace data. To achieve an accurate and long trace, trace collection hardware is designed. The flying cache simulator is attached to the tracing system to simulate various cache systems during the execution of an application program. The tracing system designed, called the Reconfigurable Address Collector and Flying Cache Simulator (RACFCS), can generate accurate and long traces and simulate the cache system for a long execution time.

Power-aware deterministic block allocation for low-power way-selective cache structure

This paper proposes a power-aware cache block allocation algorithm for the way-selective set-associative cache on embedded systems to reduce energy consumption without additional delay or performance degradation. For this goal, way selection logic and specialized replacement policy are designed to enable only one way of set-associative cache as in the direct-mapped cache. Overall cache access time becomes almost the same as that of a conventional set associative cache with accessing additional way selection logic. Because data array can be accessed without waiting for tag comparison, multiplexer delay can be removed totally. The simulation result shows that the proposed architecture can reduce a per access power consumption by 59% over conventional set-associative caches with average 0.06% of negligible performance loss.

Performance comparison of various cache systems for texture mapping

Texture mapping is commonly used to make images realistic in most current graphics systems. Texture mapping, however, requires high memory bandwidth and low memory latency to obtain good performance. Recently, a few studies have been carried out to use a cache memory system in texture mapping in older to overcome these problems and those studies show that the cache is useful for texture mapping. Miss distribution of texture cache is analyzed and we find out that quite a few conflict misses occurred by period. Considering this fact, cache systems such as Victim, Half and Half and Cooperative cache which are known to be effective to reduce conflict misses, are evaluated and compared to each other. Performance evaluation is carried out through trace-driven simulation using the DineroIII, and the results reveal that victim cache also has cost-performance effectiveness in texture mapping.

A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure

A dual data cache system structure, called a cooperative cache system, is designed as a low power cache structure for embedded processors. The cooperative cache system consists of two caches, i.e., a direct-mapped temporal oriented cache (TOC) and a four-way set-associative spatial oriented cache (SOC). These two caches are constructed with different block sizes as well as associativities. The block size of the TOC is 8bytes and that of the SOC is 32bytes, and the capacity of each cache is 8Kbytes. The cooperative cache system achieves improvement in performance and reduces power consumption by virtue of the structural characteristics of the two caches designed inherently to help each other. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor that is going to be manufactured by Samsung Electronics Co. with 0.25µm technology.

An improved lookahead instruction prefetching

A new lookahead instruction prefetching mechanism is proposed in this paper. Though significant performance improvement can be obtained by improving both the cache miss ratio and average access time for successfully prefetched blocks, most conventional prefetching mechanisms improve only one out of the two factors. To achieve balanced improvement of the two factors, a lookahead prefetching scheme that fetches multiple blocks for a prefetch request and adopts prefetch on miss mechanism is proposed. Performance evaluation is carried out through the trace-driven simulation and the proposed prefetch scheme reduces 32%/spl sim/56% of the memory access delay time of the cache system that does not perform any prefetching.

An advanced filtering TLB for low power consumption

This research is to design a new two-level TLB (translation look-aside buffer) architecture that integrates a 2-way banked filter TLB with a 2-way banked main TLB. One of the main objectives is to reduce power consumption in embedded processors by distributing the accesses to the TLB entries across several banks in a balanced manner. Thus, an advanced filtering technique is devised to reduce power dissipation by adopting a sub-bank structure at the filter TLB. And also a bank-associative structure is applied to each level of the TLB hierarchy. Simulation result shows that the miss ratio and Energy*Delay product can be improved by 59.26% and 24.9%, respectively, compared with a micro TLB with 4-32 entries, and 40.81% and 12.18%, compared with a micro TLB with 16-32 entries.

Cooperative Cache System: A Low Power Cache System for Embedded Processors

This paper presents a dual data cache system structure, called a cooperative cache system, that is designed as a low power cache structure for embedded processors. The cooperative cache system consists of two caches, i.e., a direct-mapped temporal oriented cache (TOC) and a four-way set-associative spatial oriented cache (SOC). The cooperative cache system achieves improvement in performance and reduction in power consumption by virtue of the structural characteristics of the two caches designed inherently to help each other. An evaluation chip of an embedded processor having the cooperative cache system is manufactured by Samsung Electronics Co. with 0.25 um 4-metal process technology.

A selective filter-bank TLB system [embedded processor MMU for low power]

We present a selective filter-bank translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks with a small two-bank buffer, called a filter-bank buffer, located above its associated bank. Either a filter-bank buffer or a main bank TLB can be selectively accessed, based on two bits in the filter-bank buffer. Energy savings are achieved by reducing the number of entries accessed at a time, by using filtering and the bank mechanism. The overhead of the proposed TLB turns out to be negligible compared with other hierarchical structures. Simulation results show that the energy/spl times/delay product can be reduced by about 88% compared with a fully -associative TLB, 75% with respect to a filter-TLB, and 51% relative to a banked-filter TLB.

Analyzing instruction prefetching techniques via a cache performance model: effectiveness and limitations

Instruction prefetching methods are analyzed using a cache performance model. Improvement in performance achieved by using an instruction prefetching method is classified into two factors: the number of cache misses reduced by prefetching and the average amount of miss penalty reduced by successful prefetches. Conventional instruction prefetching methods are analyzed based on these two factors. Results show that the amount of miss penalty reduced by successful prefetches, called prefetch efficiency, is more crucial in obtaining a significant improvement in performance than the number of cache misses reduced by a given prefetching method. The effectiveness and limitations of conventional methods used to increase prefetch efficiency are examined using the analytical model and simulation. The analysis reveals that any effective instruction prefetching technique should be designed by utilizing the architectural characteristics of the underlying memory system as an important fundamental direction to achieve significant performance improvement required for future high performance systems.