Kil-Whan Lee
Samsung
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Publication
Featured researches published by Kil-Whan Lee.
international solid-state circuits conference | 2013
Yong-Ha Park; Chang-Hyo Yu; Kil-Whan Lee; Hyun-Suk Kim; Youngeun Park; Chunho Kim; Yun-seok Choi; Jinhong Oh; Chang-Hoon Oh; Gurnrack Moon; Sangduk Kim; Horang Jang; Jin-Aeon Lee; Chinhyun Kim; Sungho Park
72.5GFLOPS GPGPU computing, 240 Mpixel/s sustainable image signal processing and 60fps 1080p multi-format video codec (MFC) capabilities are integrated with an 1.7GHz out-of-order-execution dual-core ARMv7A architecture CPU and 12.8GB/s memory subsystem for a next-generation application processor. The GPU-based general-purpose computing capability can deliver 10× higher energy efficiency in compute-intensive multimedia applications, compared with a CPU solution on the same die. The improved energy efficiency with GPGPU computing enables next-generation fused multimedia applications, with the assistance of dedicated high-performance low-power multimedia accelerators, as well as with low-power design and process technology, as shown in Fig. 9.4.1.
international soc design conference | 2009
Young-Jin Chung; Kil-Whan Lee; Jin-Aeon Lee; Yong-Surk Lee
In this paper, we introduce 3D graphics cache system to increase memory utilization and solve a memory bottleneck problem for an embedded system. We propose a novel pixel cache and a texture cache for a mobile 3D graphics hardware accelerator. The pixel cache enhances rendering performance by adopting a new write back algorithm and the texture cache also enhances the performance by adopting a multi-level, multi-port and non-blocking architecture. And all caches are optimized for AMBA3.0 AXI on-chip bus protocol. Also the proposed cache architecture can alleviate the memory bottleneck problem by preventing intensive memory accesses and improving cache efficiency by implementing novel cache architectures and multiple outstanding transactions. Also we can reduce a peak power which is a critical problem for an embedded system. We have evaluated the new proposed caches on 3D graphics IP on a SOC environment in where various IPs are embedded. The simulation results show the effectiveness of the proposed methods.
Archive | 2006
Young-Jin Chung; Kil-Whan Lee; Mahn-Gee Park
Archive | 2006
Young-Jin Chung; Kil-Whan Lee
Archive | 2015
Cheolkyoo Kim; Kil-Whan Lee; Yong-Ha Park
Archive | 2007
Young-Jin Chung; Kil-Whan Lee
Archive | 2006
Kil-Whan Lee; Young-Jin Chung
Archive | 2006
Young-Jin Chung; Kil-Whan Lee
Archive | 2015
Hyo-Eun Kim; Chang-Hyo Yu; Seok-Hoon Kim; Yong-Ha Park; Kil-Whan Lee
Archive | 2014
Kil-Whan Lee; Yong-Kwon Cho