Giacinto Paolo Saggese

Carry-save Montgomery modular exponentiation on reconfigurable hardware

In this paper we present a hardware implementation of the RSA algorithm for public-key cryptography. Basically, the RSA algorithm entails a modular exponentiation operation on large integers, which is considerably time-consuming to implement. To this end, we adopted a novel algorithm combining the Montgomerys technique and the carry-save representation of numbers. A highly modular, bit-slice based architecture has been designed for executing the algorithm in hardware. We also propose an FPGA-based implementation of the architecture developed. The characteristics of the algorithm, the regularity of the architecture, and the data-flow aware placement of the FPGA resources resulted in a considerable performance improvement, as compared to other implementations presented in the literature.

FPGA-Based Implementation of a Serial RSA Processor

In this paper we present an hardware implementation of the RSA algorithm for public-key cryptography. The RSA algorithm consists in the computation of modular exponentials on large integers, that can be reduced to repeated modular multiplications. We present a serial implementation of RSA, which is based upon an optimized version of the RSA algorithm originally proposed by P.L. Montgomery (1985). The proposed architecture is innovative, and it widely exploits specific capabilities of Xilinx programmable devices. As compared to other solutions in the literature, the proposed implementation of the RSA processor has smaller area occupation and comparable performance. The final performance level is a function of the serialization factor We provide a thorough discussion of design tradeoffs, in terms of area requirements vs performance, for different values of the key length and of the serialization factor.

Exploring the design-space for FPGA-based implementation of RSA

Abstract In this paper, we present two alternative architectures for implementing the Rivest–Shamir–Adleman (RSA) algorithm on reconfigurable hardware. Both architectures are innovative, especially with respect to the implementation of modular multiplication. As to the area vs time trade-off, the two solutions are at the extremes of the design-space, since one adopts a word serial approach, while the other has a fully parallel organization. Based on the analysis of these architectures for different values of the serialization factor, we explore the design-space for the field-programmable gate array (FPGA)-based implementation of the RSA algorithm. We systematically analyze and compare the results of the two design processes with respect to two fundamental metrics, namely execution time and FPGA resource usage. We emphasize pros and cons and comment trade-offs of the two design alternatives.

An FPGA-based key-store for improving the dependability of security services

A key-store is a facility for storing sensitive information, most typically the keys of a cryptographic application which provides a security service. In this paper, we present a hardware implemented key-store, which allows secure storage and high performance retrieval of RSA keys. Since RSA is the most widely adopted standard for cryptographic keys, our key-store can be effectively used to improve the dependability of a wide class of security services. Tfie device is implemented on top of a commercial off the shelf (COTS) programmable hardware board, namely a Celoxica RCWOO mounting a Xilinx Virtex-E 2000 FPGA part. We describe the architecture of the hardware device, illustrate the organization of the associated device driver, and evaluate the security and performance gain which can be achieved by integrating our device in real-world applications.

A tamper resistant hardware accelerator for RSA cryptographic applications

This paper presents an hardware accelerator which can effectively improve the security and the performance of virtually any RSA cryptographic application. The accelerator integrates two crucial security- and performanceenhancing facilities: an RSA processor and an RSA key-store. An RSA processor is a dedicated hardware block which executes the RSA algorithm. An RSA key-store is a dedicated device for securely storing RSA key-pairs. We chose RSA since it is by far the most widely adopted standard in public key cryptography. We describe the main functional blocks of the hardware accelerator and their interactions, and comment architectural solutions we adopted for maximizing security and performance while minimizing the cost in terms of hardware resources. We then present an FPGA-based implementation of the proposed architecture, which relies on a Commercial Off The Shelf (COTS) programmable hardware board. Finally, we evaluate the system in terms of performance and chip area occupation, and comment the design trade-offs resulting from different levels of parallelism.

A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations

This paper presents a technique for automatic synthesis of high-performance FPGA-based computing machines from C language source code. It exploits data-parallelism present in source code, and its approach is based on hardware application of techniques for automatic loop transformations, mainly designed in the area of optimizing compilers for parallel and vector computers. Performance aspects are considered in early stage of design, before low-level synthesis process, through a transformation-intensive branch-and-bound approach, that searches design space exploring area-performance tradeoffs. Furthermore optimizations are applied at architectural level, thus achieving higher benefits with respect to gate-level optimizations, also by means of a library of hardware blocks implementing arithmetic and functional primitives. Application of the technique to partial and complete unrolling of a Successive Over-Relaxation code is presented, with results in terms of effectiveness of area-delay estimation, and speed-up for the generated circuit, ranging from 5 and 30 on a Virtex-E 2000-6 with respect to a Intel Pentium 3 1GHz.

Using Web Services Technology for Inter-Enterprise Integration of Digital Time Stamping

This paper describes the results of a research activity con- ducted cooperatively by an academic and an industrial party. It presents a practical solution for and an experience in the implementation of time stamping services and their exposition to the Internet for inter-enterprise integration. State-of-the-art time stamping algorithms and crucial issues related to their practical implementation are discussed. Focus is on in- tegration problems which arise when a potentially large community of enterprises - which rely on a handful of heterogeneous technologies - is willing to access remote third-party time stamping services. We pro- pose a practical architecture which provides time stamping services, both in terms of relative temporal authentication, based on a linear linking scheme, and of absolute temporal authentication, based on publishing mechanisms as well as on a trusted time source. The architecture has been implemented using the emerging Web Services technology. An in- tegration experiment has been conducted to evaluate the effectiveness of the proposed solution.

Shuffled serial adder: an area-latency effective serial adder

The shuffled adder, a novel serial adder with a latency proportional to log/sub 2/N, where N is the operand width, is presented. It is derived from the Kogge-Stone adder, reordering the cells to obtain a slice-based structure that allows an area-time effective serial implementation. It can be fed with parallel inputs and produce parallel outputs, differently from the digit-serial approach that results in the need for a data-formatter to convert a parallel input into digits, and to collect the digits of the output word. A standard-cell VLSI implementation for different values of N is presented: area-time performances are evaluated through circuit simulations, and compared with digit-serial adders with various digit-size, proving the attractiveness of the proposed structure.

Architecture and FPGA Implementation of a Digit-serial RSA Processor

In the recent years, we have witnessed an increasing deployment of hardware devices for providing security functions via cryptographic algorithms. In fact, hardware devices provide both high performance and considerable resistance to tampering attacks, and are thus ideally suited for implementing computationally intensive cryptographic routines which operates on sensitive data. Among the various techniques found in the cryptography realm, the RivestShamir-Adleman (RSA) algorithm [1] constitutes the most widely adopted public-key scheme. In particular, it is useful for security applications which need confidentiality, authentication, integrity, and non-repudiation [2]. The basic operation of this algorithm is modular exponentiation on large integers,