Antonio G. M. Strollo

Dual-tree error compensation for high performance fixed-width multipliers

In this paper, a new error-compensation network for fixed-width multipliers is proposed. The error-compensation block is composed of two summation trees which are optimally chosen in order to minimize either the mean-square error or the maximum absolute error. The new technique substantially improves error performances with respect to previously proposed approaches. Simulation results show that new fixed-width multipliers exhibit significant improvements both in propagation delay and in power dissipation with respect to previous solutions.

High-performance direct digital frequency synthesizers using piecewise-polynomial approximation

This paper presents new techniques to implement direct digital frequency synthesizers (DDFSs) with optimized piecewise-polynomial approximation. DDFS performances with piecewise-polynomial approximation are first analyzed, providing theoretical upperbounds for the spurious-free dynamic range (SFDR), the maximum absolute error, and the signal-to-noise ratio. A novel approach to evaluate, with reduced computational effort, the near optimal fixed-point coefficients which maximize the SFDR is described. Several piecewise-linear and quadratic DDFS are implemented in the paper by using novel, single-summation-tree architectures. The tradeoff between ROM and arithmetic circuits complexity is discussed, pointing out that a sensible silicon area reduction can be achieved by increasing ROM size and reducing arithmetic circuitry. The use of fixed-width arithmetic can be combined with the single-summation-tree approach to further increase performances. It is shown that piecewise-quadratic DDFSs become effective against piecewise-linear designs for an SFDR higher than 100 dBc. Third-order DDFSs are expected to give advantages for an SFDR higher than 180 dBc. The DDFS circuits proposed in this paper compare favorably with previously proposed approaches.

A fast time-domain algorithm for the simulation of switching power converters

An efficient algorithm for the simulation of switched-mode power converters is developed. A Chebyshev series expansion is used to effectively solve the differential equations describing the system in each topology. The power of the new simulation technique lies both in the simple, but accurate, polynomial approximation for the state transition matrices and in the ability to explicitly obtain the instants at which the switching of the circuit topology takes place. The simulation technique is illustrated with reference to a simple Buck converter operating at a constant frequency. The derivation of the new algorithm is presented and its performance is analyzed. The case of a rapidly varying input forcing function is analyzed. Examples illustrating the generality and the computational efficiency of the algorithm are presented. >

Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error

Truncated multipliers compute the n most-significant bits of the n × n bits product. This paper focuses on variable-correction truncated multipliers, where some partial-products are discarded, to reduce complexity, and a suitable compensation function is added to partly compensate the introduced error. The optimal compensation function, that minimizes the mean square error, is obtained in this paper in closed-form for the first time. A sub optimal compensation function, best suited for hardware implementation, is introduced. Efficient multipliers implementation based on sub-optimal function is discussed. Proposed truncated multipliers are extensively compared with previously proposed circuits. Experimental results, for a 0.18 μm technology, are also presented.

A new SPICE model of power P-I-N diode based on asymptotic waveform evaluation

A new SPICE subcircuit model for power p-i-n diodes is proposed in this paper. The model is based on a moment-matching approximation of the ambipolar diffusion equation. It is shown that both the quasistatic model and the lumped charge model can be obtained as ion-order moment-matching approximations while new and more accurate models can be obtained from higher-order solutions. The proposed model takes into account emitter recombination in the highly doped end regions, conductivity modulation in the base and the moving-boundaries effect during reverse-recovery, showing good convergence properties and fast simulation times. Comparisons between the results of the SPICE model and both numerical device simulations and experimental results are presented.

Direct digital frequency synthesizers with polynomial hyperfolding technique

A new approach to design the phase to sine mapper of a direct digital frequency synthesizer (DDFS) is presented. The proposed technique uses an optimized polynomial expansion of sine and cosine functions to achieve either a 60-dBc spurious free dynamic range (SFDR), with a second-order polynomial, or a 80-dBc SFDR, with third-order polynomials. Polynomial computation is done by using new canonical-signed-digit (CSD) hyperfolding technique. This approach exploits all the symmetries of polynomials parallel computation and uses CSD encoding to minimize hardware complexity. CSD hyperfolding technique is also presented in the paper. The performances of new DDFS compares favorably with circuits designed using state-of-the-art Cordic algorithm technique.

A novel high-speed sense-amplifier-based flip-flop

A new sense-amplifier-based flip-flop is presented. The output latch of the proposed circuit can be considered as an hybrid solution between the standard NAND-based set/reset latch and the NC-/sup 2/MOS approach. The proposed flip-flop provides ratioless design, reduced short-circuit power dissipation, and glitch-free operation. The simulation results, obtained for a 0.25-/spl mu/m technology, show improvements in the clock-to-output delay and the power dissipation with respect to the recently proposed high-speed flip-flops. The new circuit has been successfully employed in a high-speed direct digital frequency synthesizer chip, highlighting the effectiveness of the proposed flip-flop in high-speed standard cell-based applications.

Optimal ON-resistance versus breakdown voltage tradeoff in superjunction power devices: a novel analytical model

A two-dimensional (2-D) analytical model for the calculation of breakdown voltage of recently proposed power super-junction (SJ) devices is presented. The model is able to correctly estimate electric field and breakdown voltage giving a deep insight in the design of SJ structures. Design criteria to minimize ON-resistance for a given breakdown voltage are discussed. Numerical 2-D simulations validate the proposed model.

Booth folding encoding for high performance squarer circuits

Combined Booth encoding and folding techniques are proposed to design squarer circuits using either carry-save or Wallace tree addition techniques. The Booth-folded technique is compared with previous state of the art squarer architectures, showing that a remarkable improvement in timing, power and area performances can be gained both for carry-save and Wallace tree cases. Experimental results, that use built-in-self-test for measuring on chip squarer performance, are presented. The measurements confirm the advantages of the Booth-folded architecture.

A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS

Spread spectrum clocking is an effective solution to reduce the electromagnetic interference produced by digital chips, using a clock signal with a frequency that is intentionally swept (frequency modulated) within a certain frequency range, with a predefined modulation profile. We present the implementation of an all-digital spread spectrum clock generator. The circuit is realized by using a design flow completely based on standard cells and is able to perform clock spreading with an arbitrary modulation profile and a modulation frequency up to 5 MHz. The circuit uses two digitally controlled delay lines driven by a digital modulator to synthesize the output waveform. A replica delay line is employed in a real-time measurement circuit to track process, voltage and temperature variations. A chip has been implemented in a 65 nm CMOS technology. The chip is able to generate signals up to 1.27 GHz. The measured peak level reduction of the clock spectrum, at 750 MHz output frequency, is 20.5 dB with a 6% modulation depth. The power dissipation is 44 mW @ 1.27 GHz.