Giacomo Valente

HEPSYCODE-RT: a Real-Time Extension for an ESL HW/SW Co-Design Methodology

This work focuses on the definition of a methodology for handling embedded real-time applications, starting from an existing HW/SW co-design methodology able to support the design of dedicated heterogeneous parallel systems. The state-of-the-art related to similar tools and methodologies is presented and the reference framework with the proposed extension to the realtime world is introduced. A case study is then described to show a design space exploration able to consider such an extension.

Criticality-aware Design Space Exploration for Mixed-Criticality Embedded Systems

This work focuses on Design Space Exploration for embedded systems based on heterogeneous parallel architectures and subjected to mixed-criticality constraints. In particular, it presents a criticality-aware evolutionary approach integrated into a reference Electronic System Level HW/SW Co-Design flow

A design methodology for soft-core platforms on FPGA with SMP Linux, OpenMP support, and distributed hardware profiling system

In recent years, the use of multiprocessor systems has become increasingly common. Even in the embedded domain, the development of platforms based on multiprocessor systems or the porting of legacy single-core applications are frequent needs. However, such designs are often complicated, as embedded systems are characterized by numerous non-functional requirements and a tight hardware/software integration. This work proposes a methodology for the development and validation of an embedded multiprocessor system. Specifically, the proposed method assumes the use of a portable, open source API to support the parallelization and the possibility of prototyping the system on a field-programmable gate array. On this basis, the proposed flow allows an early exploration of the hardware configuration space, a preliminary estimate of performance, and the rapid development of a system able to satisfy the design specifications. An accurate assessment of the actual performance of the system is then enforced by the use of an hardware-based profiling subsystem. The proposed design flow is described, and a version specifically designed for LEON3 processor is presented and validated. The application of the proposed methodology in a real case of industrial study is then presented and analyzed.

A framework for integrated monitoring of real-time embedded SoC

The presented Ph.D. work deals with the development of a framework to support the design of embedded systems. In particular, it focuses on the development of a unobtrusive profiling system to support, at run-time, both the definition of the best execution platform and its resource optimization. The final goal is the definition of a framework exploiting reconfigurable logic, based on monitoring actions and run-time decisions. The profiling system under development and its high portability toward different architectures, representing current status of Ph.D. work, are described. Planned future steps, including benchmarking by means of industrial applications, are illustrated.

CC4CS: an Off-the-Shelf Unifying Statement-Level Performance Metric for HW/SW Technologies

Outlining the general characteristics of embedded systems is an arduous task. In fact, the design of such kind of systems is heavily influenced by functional and non-functional requirements, and it is based on quite complex design flows. So, there is often the need to adopt a HW/SW co-design methodology able to support the designers during high-level phases so that they can perform early analysis before dealing with low-level ones. Such a methodology, to be effective, should consider also performance estimation and ESL HW/SW timing co-simulation. The goal of this paper is to introduce a novel and fast performance metric able to speed-up the early analysis and design space exploration to identify the more promising architectures for different application domains. In particular, the paper presents a framework to evaluate such a metric and to perform some preliminary analysis to evaluate its meaningfulness when exploited in the HW/SW domain.

Criticality-driven Design Space Exploration for Mixed-Criticality Heterogeneous Parallel Embedded Systems

Heterogeneous platforms are becoming widely diffused in the embedded system area, mainly because of the opportunities to increase application execution performance and, at the same time, to optimize other orthogonal metrics. In such a context, the introduction of mixed-criticality constraints, while considering heterogenous parallel architectures, creates new challenges to industrial and academic research. The main design issue is related to a Design Space Exploration (DSE) approach able to cope with mixed-criticality constraints that typically limits the number of feasible solutions. So, this work1 focuses on DSE for embedded systems based on heterogeneous parallel architectures and subjected to mixed-criticality constraints. In particular, it presents a criticality-driven evolutionary approach integrated into a reference Electronic System Level HW/SW Co-Design flow to support the designer of mixed-criticality embedded systems.

Time Bands: A Software Approach for Timing Analysis on Resource Constrained Systems

Timing analysis of embedded systems is an operation performed when there are tasks that have to execute with a well precise deadline, and need to be scheduled, such as those on real-time systems. The diffusion of embedded systems to different kind of application areas is driving platforms toward heterogeneous multi-core architectures, that require a timing analysis done by using measurement based techniques. Measurements collection, when done via an instrumentation of the application, can cause an overhead in the execution time, footprint and necessary space to store data, that can affect the behaviour of the system. In such a scenario, this work proposes a framework that allows a user to quickly perform instrumentation choices, by using a concept named Time Band, and to have a direct feedback about the impact of its choices on some performance parameters. Time Band is then applied to Rapitime, a diffused timing analysis tool, and first tests have been done on IA-32 and PowerPC architectures, showing the advantages of different techniques the can be applied to realize the framework.

Design and validation of multi-core embedded systems under time-to-prototype and high performance constraints

This work deals with the problem of developing embedded multi-core systems, under time-to-prototype and high performance constraints, by exploiting reconfigurable logic. In particular, the paper focuses on the early analysis activities, performed by means of native simulation technologies, and then on the full development of an embedded multi-core platform composed of four LEON3 soft-processors and able to support the execution of OpenMP based applications. Moreover, in order to evaluate software execution time at run-time, a distributed hardware profiling mechanism has been inserted into the final implementation to monitor the whole system. The final goal is the definition and the exploitation of a high-level design and validation methodology able to exploit both a well-known parallel execution paradigm and a run-time system monitoring service. Correctness and performance of such a platform have been evaluated by means of specific benchmarks.