Luigi Pomante

Metrics for design space exploration of heterogeneous multiprocessor embedded systems

This paper considers the problem of designing heterogeneous multiprocessor embedded systems. The focus is on a step of the design flow: the definition of innovative metrics for the analysis of the system specification to statically identify the most suitable processing elements class for each system functionality. Experimental results are also included, to show the applicability and effectiveness of the proposed methodology.

Reliability Properties Assessment at System Level: A Co-Design Framework

This paper introduces an enhanced hardware/software co-design framework allowing the designer to introduce hardware fault detection properties in the system under consideration. By considering reliability requirements at system level, within a hw/sw co-design flow, it is possible to evaluate overheads and benefits of different solutions. System specification, hardware and software concurrent fault detection design methodologies and hw/sw partitioning are the three key factors taken into account. The paper discusses these aspects providing a complete overview of the reliability co-design project.

Affinity-driven system design exploration for heterogeneous multiprocessor SoC

Continuous advances in silicon technology enable the development of complex system-on-chip as cooperation among digital signal processors (DPSs), general purpose processors (GPPs), and specific hardware components. The impact of this choice is not only limited to the target architecture, but also encompasses the overall system specification. It is thus crucial to manage such a complexity using high-level specification languages and a tool chain supporting the designer throughout a set of strategic decisions, such as the identification of a set of possible target architectures, the verification of the correctness of the specification, and the partitioning of the specification onto a set of computational resources. This paper addresses this type of problem by proposing a design flow supporting the system-level design of heterogeneous multiprocessor system-on-chip (MP-SoC), by extracting information from the system description (e.g., SystemC) - statically and in a fast manner - and by providing a set of quantitative measures correlating the type of executor, the functionality, and a timing estimation. Partitioning and architecture selection are built on top of this data and the final analysis of the selected hardware-software solution over the identified candidates is finally submitted to a timing verification via simulation. Note that the possibility of actually performing a comprehensive design space exploration, in general, is tightly influenced by the interaction between partitioning/architecture-selection and timing simulation in the design flow; for this reason, the description of this aspect is particularly emphasized in the presentation of the methodology. To show the applicability of the proposed methodology, two relevant case studies are described in the paper.

A multi-level strategy for software power estimation

In this paper a comprehensive methodology for software power estimation is presented. The methodology is supported by rigorous mathematical models of power consumption at three different levels of abstraction. The methodology has been validated in a complete framework developed within the TOSCA co-design environment.

System-level design space exploration for dedicated heterogeneous multi-processor systems

This work faces the problem of the HW/SW co-design of dedicated systems based on heterogeneous multi-processor architectures. In particular, it proposes a system-level design space exploration approach that allows the related co-design methodology to suggest an HW/SW partitioning of the application specification and a mapping of the partitioned entities onto an automatically selected heterogeneous multi-processor architecture. The modeling strategy and the description of the adopted heuristic and metrics represent the core of the paper while a simple case study allows clarifying the main features of the whole approach.

Agent-based scalable design of a cross-layer security framework for Wireless Sensor Networks Monitoring Applications

Secure monitoring services supported by flexible, manageable, and cheap systems in areas where ordinary networks are unsuitable: this is one of to-day challenges in health monitoring engineering. Wireless Sensor Networks represent a promising technological solution but resource constraints and exposure to external attacks could limit their employment. The design and the implementation of an effective security to provide the monitoring service with the reasonable level of reliability is the scope of this paper. Following the platform-based design methodology, we have designed and implemented a “Secure Platform” to support Monitoring Applications which is compliant to requirements such as modularity, optimized usage of resource, solution scalability. To this aim, the Secure Platform exploits mobile agents and we have enhanced middleware solutions already available in literature. Security functions implemented in the Secure Platform have been a distributed intrusion detection system, based on a simplified approach to Hidden Markov Models, supported by an hybrid cryptographic scheme, based on network topology authentication. These security functions have been proposed by the same authors in [12] and [13]. Detailed design and the description of the software enhancements to the middleware platform are presented in this paper.

A spatial extension of TinyDB for wireless sensor networks

The ability to run spatial queries is extremely useful for wireless sensor networks. Spatial query execution has been extensively studied in the context of centralized spatial databases; however because of the energy and bandwidth limitation of sensor nodes these solutions are critical to wireless sensor networks. In this paper, we propose an extension of TinyDB suitable to manage the location of sensor nodes and, hence, able to process besides standard queries, spatial queries as well. The proposal has been implemented and validated.

Reliable System Specification for Self-Checking Data-Paths

The design of reliable circuits has received a lot of attention in the past, leading to the definition of several design techniques introducing fault detection and fault tolerance properties in systems for critical applications/environments. Such design methodologies tackled the problem at different abstraction levels, from switch-level to logic, RT level, and more recently to system level. The aim of this paper is to introduce a novel system-level technique based on the redefinition of the operator functionality in the system specification. This technique provides reliability properties to the system data path, transparently with respect to the designer. Feasibility, fault coverage, performance degradation and overheads are investigated on a FIR circuit.

Reliability properties assessment at system level: a co-design framework

The reliability co-design project aims at integrating in a standard hw/sw co-design flow the elements for achieving a final system able to detect the occurrence of a fault during its operational life. The paper presents the focus of the project, the definition and identification of design methodologies for implementing the nominal, checking and checker functionalities either in hardware or in software. An outline of the system specification and system partitioning aspects is also provided.

Exploiting WSN for Audio Surveillance Applications: The VoWSN Approach

This paper focuses on the analysis of fundamental issues which has to be considered in order to gain voice from a wireless sensor network (WSN) that is assumed to be constituted by MicaZ wireless sensor nodes. Problems related to the transport of an audio signal through a wireless channel and sensor nodes are thus analyzed and a project for an audio surveillance system is presented.