Giovanni A. Salvatore

Wafer-scale design of lightweight and transparent electronics that wraps around hairs

Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-μm thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12 V and above 1 MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

Fabrication and transfer of flexible few-layers MoS2 thin film transistors to any arbitrary substrate.

Recently, transition metal dichalcogenides (TMDCs) have attracted interest thanks to their large field effective mobility (>100 cm(2)/V · s), sizable band gap (around 1-2 eV), and mechanical properties, which make them suitable for high performance and flexible electronics. In this paper, we present a process scheme enabling the fabrication and transfer of few-layers MoS2 thin film transistors from a silicon template to any arbitrary organic or inorganic and flexible or rigid substrate or support. The two-dimensional semiconductor is mechanically exfoliated from a bulk crystal on a silicon/polyvinyl alcohol (PVA)/polymethyl methacrylane (PMMA) stack optimized to ensure high contrast for the identification of subnanometer thick flakes. Thin film transistors (TFTs) with structured source/drain and gate electrodes are fabricated following a designed procedure including steps of UV lithography, wet etching, and atomic layer deposited (ALD) dielectric. Successively, after the dissolution of the PVA sacrificial layer in water, the PMMA film, with the devices on top, can be transferred to another substrate of choice. Here, we transferred the devices on a polyimide plastic foil and studied the performance when tensile strain is applied parallel to the TFT channel. We measured an electron field effective mobility of 19 cm(2)/(V s), an I(on)/I(off)ratio greater than 10(6), a gate leakage current as low as 0.3 pA/μm, and a subthreshold swing of about 250 mV/dec. The devices continue to work when bent to a radius of 5 mm and after 10 consecutive bending cycles. The proposed fabrication strategy can be extended to any kind of 2D materials and enable the realization of electronic circuits and optical devices easily transferrable to any other support.

Metal-Ferroelectric-Meta-Oxide-semiconductor field effect transistor with sub-60mV/decade subthreshold swing and internal voltage amplification

This work reports the first complete experimental demonstration and investigation of subthreshold swing, SS, smaller than 60 mV/decade, at room temperature, due to internal voltage amplification in FETs with a Metal-Ferroelectric-Metal-Oxide gate stack. The investigated p-type MOS transistor is a dedicated test structure to explore the negative capacitance effect by probing the internal voltage between the P(VDF-TrFE) and SiO2 dielectric layers of the gate stack. We find that the region of internal surface potential amplification, dψS/dVg>1, corresponds to an S-shape of the polarization versus ferroelectric voltage (associated with negative capacitance). In Fe-FETs the internal voltage amplification could significantly lower their SS, even without reaching sub-60mV/dec values. SSmin as low as 46 to 58 mV/decade and average swings, SSavg, as small as 51 to 59 mV/dec are observed for the first time in a minor loop hysteretic characteristics of Fe-FETs.

Flexible Self-Aligned Amorphous InGaZnO Thin-Film Transistors With Submicrometer Channel Length and a Transit Frequency of 135 MHz

Flexible large area electronics promise to enable new devices such as rollable displays and electronic skins. Radio frequency (RF) applications demand circuits operating in the megahertz regime, which is hard to achieve for electronics fabricated on amorphous and temperature sensitive plastic substrates. Here, we present self-aligned amorphous indium-gallium-zinc oxide-based thin-film transistors (TFTs) fabricated on free-standing plastic foil using fabrication temperatures . Self-alignment by backside illumination between gate and source/drain electrodes was used to realize flexible transistors with a channel length of 0.5 μm and reduced parasitic capacities. The flexible TFTs exhibit a transit frequency of 135 MHz when operated at 2 V. The device performance is maintained when the TFTs are bent to a tensile radius of 3.5 mm, which makes this technology suitable for flexible RFID tags and AM radios.

Demonstration of subthrehold swing smaller than 60mV/decade in Fe-FET with P(VDF-TrFE)/SiO 2 gate stack

This work experimentally demonstrates, for the first time, that by integrating a thin ferroelectric layer into a gate stack of a standard MOS transistor one, it is possible to overcome the 60 mV/decade subthreshold swing limit at room temperature of MOSFET. We find sub-threshold swings as low as 13 mV/decade in Fe-FETs with 40 nm P(VDF-TrFE)/SiO2 gate stack. The mechanism governing the low subthreshold swing in Fe-FET transistors is the negative capacitance of the ferroelectric layer that provides voltage amplification; with our particular ferroelectric gate stack we report for the first time negative capacitance at room temperature.

Experimental confirmation of temperature dependent negative capacitance in ferroelectric field effect transistor

In this paper, we report the basic design conditions and the experimental confirmation of a temperature dependent negative capacitance (NC) effect in a ferroelectric field-effect-transistor (Fe-FET). We find that the internal voltage amplification peaks of a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure are correlated with the S-shape of the polarization versus electrical field characteristics. The internal voltage amplification is responsible for the subthreshold swing reduction in a Fe-FET; this effect cancels out when the temperature is increased close to the Curie temperature because of the narrowing of the NC region and because of the saturation of the amplification. A counter-clockwise rotation of the P-V loops with an associated increase of the dP/dV slope with the temperature is reported, which corresponds to an increase of the overall ferroelectric capacitance with the temperature. Finally, we theoretically and experimentally demonstrate that an optimum temperature exists at which the amplification gets its maximum

Ultra low power: Emerging devices and their benefits for integrated circuits

In this paper we analyze and discuss the characteristics and expected benefits of some emerging device categories for ultra low power integrated circuits. First, we focus on two categories of sub-thermal subthreshold swing switches Tunnel FETs and Negative Capacitance (NC) FETs and evaluate their potential advantages for digital and analog design, compared to CMOS. Second, we investigate the combined low power and novel integrated functionality in some hybrid Nano-Electro-Mechanical (NEM) devices: the Resonant Body (RB) Fin FET for nW time reference ICs and dense arrays of Suspended Body (SB) Double Gate (DG) Carbon Nanotube (CNT) FET for low power analog/RF and integrated sensor arrays.

IGZO TFT-Based All-Enhancement Operational Amplifier Bent to a Radius of 5 mm

An all-enhancement operational amplifier operating at 5 V and comprising 16 n-type amorphous indium-gallium-zinc-oxide thin-film transistors (TFTs) is fabricated on a 50 μm thick flexible polyimide substrate. The operational amplifier has an open loop voltage gain of 18.7 dB and a unity-gain frequency of 472 kHz while the common-mode rejection ratio (CMMR) is larger than 40 dB. The mechanical flexibility of the amplifier is demonstrated by bending the circuit to a radius of 5 mm, which corresponds to a tensile strain of 0.5% parallel to the TFT channels. The bent amplifier shows the same output behavior as when flat. The power consumption of the operational amplifier is 900 μW, regardless whether the circuit is flat or bent.

Flexible Self-Aligned Double-Gate IGZO TFT

In this letter, flexible double-gate (DG) thin-film transistors (TFTs) based on InGaZnO4 and fabricated on free standing plastic foil, using self-alignment (SA) are presented. The usage of transparent indium-tin-oxide instead of opaque metals enables SA of source-, drain-, and top-gate contacts. Hence, all layers, which can cause parasitic capacitances, are structured by SA. Compared with bottom-gate reference TFTs fabricated on the same substrate, DG TFTs exhibit a by 68% increased transconductance and a subthreshold swing as low as 109 mV/dec decade (-37%). The clockwise hysteresis of the DG TFTs is as small as 5 mV. Because of SA, the source/drain to gate overlaps are as small as ≈ 1 μm leading to parasitic overlap capacitances of 5.5 fF μm-1. Therefore a transit frequency of 5.6 MHz is measured on 7.5 μm long transistors. In addition, the flexible devices stay fully operational when bent to a tensile radius of 6 mm.

Influence of Mechanical Bending on Flexible InGaZnO-Based Ferroelectric Memory TFTs

Future flexible electronic systems require memory devices combining low-power operation and mechanical bendability. Here, we present mechanically flexible amorphous InGaZnO (a-IGZO) memory thin-film transistors (TFTs) with a ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] gate insulator. Memory operation is demonstrated with a memory window of 3.2 V and a memory ON/OFF ratio of 1.5×106 (gate-source voltage sweep of ±6 V). The measured mobility of 8 cm2 V-1s-1 and the ON/OFF current ratio of 107 are comparable with the values for reference TFTs fabricated on the same substrate. To use memory TFTs in flexible applications, it is crucial to understand their behavior under mechanical strain. Flexible memory and reference TFTs are characterized under bending radii down to 5.5 mm, corresponding to tensile and compressive strain of ≈ ±0.6%. For both memory and reference TFTs, tensile strain causes negative threshold voltage shifts and increased drain currents, whereas compressive strain results in the opposite effects. However, memory TFTs, compared with reference TFTs, exhibit up to 8× larger threshold voltage shifts and 17× larger drain current variations. It is shown that the strain-dependent properties of a-IGZO can only explain the shifts observed in reference TFTs, whereas the variations in memory TFTs are mainly caused by the piezoelectric properties of P(VDF-TrFE).