Giovanni Cali

A 65 nm CMOS low power RF front-end for L1/E1 GPS/Galileo signals

In this paper, we present a low-power RF front-end designed for L1/E1 GPS/Galileo, implemented on 65 nm CMOS technology. It draws 16mA on external voltage supply of 1.2V, with power consumption of less than 20mW. The chip could work also at 1.8V using a low dropout regulator embedded in the chip. The device integrates a high performance low noise amplifier, an AGC that dont need any external capacitor and a PLL loop filter reducing the external components count: only few passives for matching and external TCXO for frequency reference are needed. A programmable synthesizer manages most of the commonly used TCXO frequencies. Two default operative modes and related reference frequencies have been defined: 16.368MHz and 26MHz. The IF filter is fully embedded. It is a complex filter characterized from two operative modes: the first for GPS-only signal, the second for both GPS and GALILEO signals. Its characteristics can be adjusted through a proper switching cascade of adaptive first order cells. The data bit for base band are generated by a 3-bits ADC. The whole die area is 2.6mm2

A low voltage RF receiver for digital satellite radio

An integrated low voltage RF receiver for the Digital Satellite Radio is presented. It uses innovative solutions for critical blocks such as LNA, IF buffer, VCO, etc., and includes power supply regulators at 2.4 V. The circuit has been integrated in a high performance 20-GHz silicon bipolar technology and correctly operates with an external power supply varying from 2.7 V to 5.5 V.An integrated low voltage RF receiver for the digital satellite radio is presented. It uses innovative solutions for critical blocks such as LNA, IF buffer, VCO, etc., and includes power supply regulators at 2.4 V. The circuit has been integrated in a high performance 20 GHz silicon bipolar technology and correctly operates with an external power supply varying from 2.7 V to 5.5 V.

A 2.3GHz SiGe RFIC front-end for U.S. satellite radio applications

A 0.35 /spl mu/m SiGe BiCMOS double-conversion digital audio satellite radio receiver with on-chip RF and IF PLL is presented. The 17mm/sup 2/ front-end has -97dBm input sensitivity, 3.5dB NF, -13dBm off-channel IIP3 at maximum RF gain and 12dBm at minimum RF gain, 35dB RF and 90dB IF gain range, with >30dB image rejection and 30dBm on-channel OIP3. The RF VCO features a phase noise of -107dBc/Hz at 100kHz offset.

A VLSI low power solution for mobile satellite radio receivers

Two ICs have been implemented as part of a mobile digital satellite radio receiver. An RF front-end stage makes a superheterodyne frequency conversion from L band to 1.84 MHz IF, with a high level of integration, i.e only a SAW filter outside the chip. A fully digital channel decoder receives the IF signal from the RF front-end and converts it by means of an integrated 6-bit half flash A/D converter. Its main functions are a QPSK demodulator, a Viterbi decoder, a Reed-Solomon decoder, a deinterleaver and TDM extraction. The analogue input signal carrier is 1.84 MHz while the maximum chip frequency is about 10 MHz in order to optimize power consumption. Output data are transferred using a serial interface at a maximum rate of 128 kbit/s, The channel decoder is implemented using a five-metal layer CMOS 0.35 /spl mu/m process, complexity is 1.5 million transistors, dissipating 50 mW with die size of 23 mm/sup 2/. For the RF front-end, implemented in a 20 GHz bipolar process, die size is 16 mm/sup 2/, power consumption is about 200 mW, and includes on-chip low noise amplifier, 3.6 GHz oscillator and two PLL loops.