Girish P. Chandranmenon

Integration of 802.11 and third-generation wireless data networks

The third-generation (3G) wide area wireless networks and 802.11 local area wireless networks possess complementary characteristics. 3G networks promise to offer always-on, ubiquitous connectivity with relatively low data rates. 802.11 offers much higher data rates, comparable to wired networks, but can cover only smaller areas, suitable for hot-spot applications in hotels and airports. The performance and flexibility of wireless data services would be dramatically improved if users could seamlessly roam across the two networks. In this paper, we address the problem of integration of these two classes of networks to offer such seamless connectivity. Specifically, we describe two possible integration approaches - namely tight integration and loose integration and advocate the latter as the preferred approach. Our realization of the loose integration approach consists of two components: a new network element called IOTA gateway deployed in 802.11 networks, and a new client software. The IOTA gateway is composed of several software modules, and with cooperation from the client software offers integrated 802.11/3G wireless data services that support seamless intertechnology mobility, Quality of Service (QoS) guarantees and multiprovider roaming agreements. We describe the design and implementation of the IOTA gateway and the client software in detail and present experimental performance results that validate our architectural approach.

Design and implementation of a WLAN/cdma2000 interworking architecture

The combination of 3G and WLAN wireless technologies offers the possibility of achieving anywhere, anytime Internet access, bringing benefits to both end users and service providers. We discuss interworking architectures for providing integrated service capability across widely deployed 3G cdma2000-based and IEEE 802.11-based networks. Specifically, we present two design choices for integration: tightly coupled and loosely coupled, and recommend the latter as a preferred option. We describe in detail the implementation of a loosely coupled integrated network which provides two kinds of roaming services, a SimpleIP service and a Mobile-IP service. We present, in detail, two new components used to build these services: a network element called a WLAN integration gateway deployed in WLAN networks; a client software on the mobile device. For a mobile device with interfaces to both technologies, our system supports seamless handoff in the presence of overlapping radio coverage.

A lock-free, cache-efficient multi-core synchronization mechanism for line-rate network traffic monitoring

Line-rate data traffic monitoring in high-speed networks is essential for network management. To satisfy the line-rate requirement, one can leverage multi-core architectures to parallelize traffic monitoring so as to improve information processing capabilities over traditional uni-processor architectures. Nevertheless, realizing the full potential of multi-core architectures still needs substantial work, especially in the face of the ever-increasing volume and complexity of network traffic. This paper addresses the issue through the design of a lock-free, cache-efficient synchronization mechanism that serves as a basic building block for a general class of multithreaded, multi-core traffic monitoring applications. We embed the synchronization mechanism into MCRingBuffer, a multi-core shared ring buffer that provides fast data accesses among threads running in different cores. MCRingBuffer allows concurrent lock-free data accesses and improves the cache locality of accessing the control variables that are used for thread synchronization. Through extensive evaluation on an Intel Xeon multi-core machine, we show that MCRingBuffer achieves a throughput gain of up to 5× over existing lock-free ring buffers. Finally, we present a parallel traffic monitoring prototype that is built upon MCRingBuffer, and demonstrate via trace-driven simulation how MCRingBuffer facilitates packet processing at line rate.

A lock-free, cache-efficient shared ring buffer for multi-core architectures

We propose MCRingBuffer, a lock-free, cache-efficient shared ring buffer that provides fast data accesses among threads running in multi-core architectures. MCRingBuffer seeks to reduce the cost of inter-core communication by allowing concurrent lock-free data accesses and improving the cache locality of accessing control variables used for thread synchronization. Evaluation on an Intel Xeon multi-core machine shows that MCRingBuffer achieves a throughput gain of up to 4.9x over existing concurrent lock-free ring buffers. A motivating application of MCRingBuffer is parallel network traffic monitoring, in which MCRingBuffer facilitates multi-core architectures to process packets at line rate.