Giuseppe Consentino

A simplified and approximate power MOSFET intrinsic capacitance simulation: Theoretical studies, measures and comparisons

This paper implements a theoretical study on power MOSFETs internal capacitances. To simulate these capacitances the paper takes into consideration the internal structures of the power MOSFETs, materials and process characteristics. Finally, real measures are implemented on a power MOSFET device by ST and are compared to the simulated data to validate the model.

Effects on power transistors of Terrestrial Cosmic Rays: Study, experimental results and analysis

High voltage power transistors used in inverters for photovoltaic panels and avionic applications are naturally exposed to Terrestrial Cosmic Rays, or Atmospheric Neutrons, which are known to induce catastrophic failures such as burnouts or gate ruptures. Accelerated tests on different power MOSFETs and IGBTs technologies were performed in ANITA neutron facility, at Uppsala, Sweden. Experimental details and results will be presented and discussed.

How the Power MOSFET Inversion layer carriers' mobility and its thermal gradient affects the TC

This paper studies the mobility of the carriers in the inversion layer of the power MOSFET and how this affects the TC (thermal coefficient). All the scattering mechanisms that are involved in the inversion layer were considered to modeling the mobility. In particular, the effect of the transverse electrical field, phonons and the Coulomb scattering effects will be studied. Particular attention will be placed on the acoustic and optical phonon effects and on the carrier-carrier scattering, ionized impurity in the depletion region, oxide fixed charges and oxide- silicon interface charges effects. The paper also will treat the Lombardi unified model to explain the mobility in the inversion layer. New considerations on TC will be implemented and a real example will validate the model proposed.

A new approach to establish the thermal instability condition and the failure time during the drain current focusing process in a power MOSFET working in linear zone

This technical article explains the thermal instability condition of a power MOSFET while it operates in linear mode considering an innovative approach. In particular, it studies the phenomenon evaluating the failure time when a drain current focusing process occurs or, simply, it evaluates the die localized increased temperature due to a hot spot creation even if no failure occurs. A theoretical model is implemented and validated by specific experimental tests.

Power MOSFETs working in linear zone: The dangerous effect of the K gain factor on thermal instability

The gain factor K of the power MOSFET is an electrical parameter that mathematically speaking connects VGS to ID. Practically, higher is K higher will be ID fixing VGS, VTH and all the others physical and electrical parameters. K is a very important electrical parameter regarding the power MOSFET working in linear operating zone. In fact, even if, typically, higher K factor needs in switching operation mode, in linear zone, instead, K must be low to avoid a possible premature failure of the device.

A New Effective Methodology for Semiconductor Power Devices HTRB Testing

An advanced high-temperature reverse bias (HTRB) testing procedure for performing reliability tests on power transistors is reported. The main target is to monitor continuously the degradation trend of tested devices. Therefore, the total HTRB test time is divided into short stress cycles. Thanks to a purposely designed miniature heater, which controls the individual case temperature of devices under test (DUTs), electrical characterization, at low or high temperature, can be performed at the end of each stress period automatically. In this way, DUTs electrical parameters can be periodically measured to identify early warnings of failure, and test can be stopped for the sole out-of-specification devices. In addition, thanks to the fast thermal control, thermal runaway processes can be inhibited, freezing the degradation state to a presettled level, in order to perform appropriate postfailure analysis. Finally, the new HTRB methodology allows for evidencing anomalous behaviors, which are not considered as failures, and the application of low frequency noise measure techniques provides the evidence of the effects of the applied thermo-electrical stress. The proposed HTRB methodology together with low frequency noise measurements are presented as well as the results obtained from the experimental application of the procedure on silicon power MOSFETs.

Anomalous failure in low-voltage p-chanel power MOSFETs during the intrinsic diode recovery time

This paper studies and analyzes the root causes of anomalous failures of low-voltage p-channel power MOSFETs during the intrinsic diode recovery time in dV/dt test. In particular, the dV/dt characterization test is described and, afterwards, specific electrical tests are provided to explain the root causes. From the electrical results point of view, the dV/dt slew rate does not involve an intrinsic bipolar transistor turn-on, as usually assumed in these kinds of failure. Instead, a gate oxide degradation occurs causing the device to fail as a result of dV/dt repetitive events. Such kinds of gate oxide degradation were observed measuring the threshold voltage degradation after an established dV/dt train of impulses till the failure occured. Afterwards, the same train of impulses was implemented on a new series of samples, changing the circuit and, in particular, inserting a resistor in the gate electrode. In this test, no failures were observed, even if several repetitive trains of impulses were supplied.