Gaetano Bazzano

Distributed Modeling of Layout Parasitics in Large-Area High-Speed Silicon Power Devices

This paper reports a technique for generating a lumped-element distributed model for silicon power devices that takes into account the effect of layout parasitics. The proposed methodology exploits the high-frequency modeling approach of microstrips and striplines to describe both the passive parts of the device and elementary transistor cells. A semi-empirical model for the elementary transistor cells of the power device is also proposed. Parameter extraction is described and validated by direct comparison with device simulations of an actual device. The proposed modeling approach is employed to investigate the internal current distribution of a high-voltage silicon power MOSFET supplied by STMicroelectronics during the turnoff transient. The tradeoff that must be accomplished between accuracy and complexity is discussed. The effect of increased switching frequency on the device current distribution is also reported explaining how it may lead to performance degradation and device failure.

Electrothermal PSpice Modeling and Simulation of Power Modules

Integrated power electronics modules (IPEMs) represent an innovative typology of power electronics assemblies able to guarantee several advantages such as increasing of power density, better management of the thermal flows, and a significant reduction of the package sizes. Their characteristics make them suitable for applications like motor drives or power conditioning. IPEM usage in emerging fields like hybrid automotive traction and electric generation from renewable energy sources is continuously increasing. In this paper, we describe the implementation of a devised flow to generate the layer-based electrothermal PSpice model of an IPEM and the simulation flow of the model. The proposed modeling methodology allows reducing an electrothermal multidomain problem to an electrical single one. The general PSpice-like nature of the proposed model makes it suitable for a wide range of simulation frameworks where the integration of heterogeneous multiphysics models could be a difficult task. The outlining of both electrical and thermal PSpice layers is discussed, and the implementation into the final model, by the assistance of custom electronic-design-automation flow, is presented. Moreover, we describe the validation procedure of the proposed approach, and the results are compared with the ones obtained by a commercial finite-element-based package used as a benchmark. Two simulation approaches related to specific conversion systems, and related issues, are presented and discussed.

Electro-thermal model of Integrated Power Electronics Modules based on an innovative layered approach

In this work, the implementation flow of an electro-thermal model of an Integrated Power Electronics Module is presented. The methodology is based on an innovative layered approach where the whole system is devised as composed by two distinct layers, an electrical and a thermal one, linked together through the active model of a discrete power MOSFET device. We describe an original methodology aimed at reducing an electro-thermal multi-domain problem to an electrical single-domain one thanks to a mapping between thermal and electrical quantities. The strong point of the proposed approach relies on the fact that layers, generated independently with the aid of FEM simulations, are then melted together in a spice-like macro model that could be used, by engineers, in a pure spice-like design environment without the aid of external mathematical solver engines. Finally, a series of simulation issues are discussed.

Modeling of thermal network in silicon power MOSFETs

In this work we propose a methodology to define an equivalent resistive thermal network that allows to model the lateral heat propagation through the silicon substrate of power devices. The basic idea is to split the substrate in basic elements of length ΔL and to associate to each element, lumped thermal resistances. The proposed model is validated by comparison with electro-thermal numerical simulations in silicon Power MOSFET technology. The proposed thermal network accurately predicts the temperature increase as a function of the distance from the heat source.

Integrated power electronics modules: Electro-thermal modeling flow and stress conditions overview

In recent years, power electronics solutions spread through fields ever less tied to a pure industrial context for embracing on-coming applications in consumer, automotive and renewable energy markets. In all those contexts several requirements drive engineers in implementing assemblies having increasingly strict constraints as high power density, optimal management of temperature, and a more and more compact and mechanically robust structure, so to guarantee a good degree of integration in the host system. In applications where the power to be managed is significant (tens to hundreds of kW), Integrated Power Electronics Modules (IPEMs) play a major role. These solutions, already extensively industrialized, well satisfy the above mentioned integration requirements, and allow the final customer to reduce power-management costs. In order to design an IPEM able to satisfy all the requirements it is necessary to have preliminary CAD models able to predict its behavior from several points of view. In this work, a layered modeling flow able to take into account both the electrical and thermal behavior is detailed. Moreover, a series of issues able to produce prospective mechanical stresses and related failure conditions are discussed.