Gjermund Kittilsland

A sub-micron particle filter in silicon

Abstract A multi-purpose screen filter structure in silicon has been fabricated and characterized. The fabrication of the filter structure is based on a two-step self-aligning process using lateral boron doping, anisotropic silicon etching and silicon dioxide undercut etching. Filters for filtration of particles down to 50 nm have been fabricated. The flow resistance for gases and liquids has been measured. The fluid passes between two electrically conducting membranes, so other applications such as fluid identification and concentration measurements are possible. A preliminary fluid identification experiment is presented.

Boron etch-stop in TMAH solutions

Abstract Etch rates of 〈100〉 single-crystal silicon in tetramethyl ammonium hydroxide (TMAH) solutions have been measured as a function of boron doping concentration with the purpose of studying the feasibility of an etch-stop. The boron concentration has been varied up to 2.5 × 1020 cm−3. An etch ratio of 1:40 between the heavily and lightly boron-doped silicon has been obtained. This ratio may depend slightly on the temperature of the etch, but no significant variation with etchant concentration has been observed for TMAH concentrations in the range 23–32 wt.%. Preliminary experiments on the effect of adding pyrazine to the etch solution indicate that pyrazine increases the etch rate slightly and seems to have the effect of reducing surface roughness.

New fluid filter structure in silicon fabricated using a self‐aligning technique

A new fluid filter structure in silicon has been designed and fabricated. The structure consists of two hole membranes of silicon displaced laterally relative to each other. The size of the largest particles which can pass through the structure is determined by the thickness of the silicon dioxide spacers separating the two hole membranes. One single‐hole pattern is used in combination with a special two‐step self‐aligning technique involving heavy boron diffusion, anisotropic silicon etching, and silicon dioxide undercut etching. Structures with membrane separation distances of 50 and 200 nm have been made. Since the structure electrically is a capacitor, other applications are possible.

High-performance long wave infrared bolometer fabricated by wafer bonding

A novel microbolometer with peak responsivity in the longwave infrared region of the electromagnetic radiation is under development at Sensonor Technologies. It is a focal plane array of pixels with a 25μm pitch, based on monocrystalline Si/SiGe quantum wells as IR sensitive material. The novelty of the proposed 3D process integration comes from the choice of several of the materials and key processes involved, which allow a high fill factor and provide improved transmission/absorption properties. Together with the high TCR and low 1/f noise provided by the thermistor material, they will lead to bolometer performances beyond those of existing devices. The thermistor material is transferred from the handle wafer to the read-out integrated circuit (ROIC) by wafer bonding. The low thermal conductance legs that connect the thermistor to the ROIC are fabricated prior to the transfer bonding and are situated under the pixel. Depending on the type of the transfer bonding used, the plugs connecting the legs to the thermistor are made before or after this bonding, resulting in two different configurations of the final structure. Using a low temperature oxide bonding and subsequent plugs formation result in through-pixel plugs. Pre-bonding plugs formation followed by thermo-compression bonding result in under-pixel plugs. The pixels are subsequently released by anhydrous vapor HF of the sacrificial oxide layer. The ROIC wafer containing the released FPAs is bonded in vacuum with a silicon cap wafer, providing hermetic encapsulation at low cost. Antireflection coatings and a thin layer getter are deposited on the cap wafer prior to bonding, ensuring high performance of the bolometer.

Fluxless wafer-level Cu-Sn bonding for micro- and nanosystems packaging

For wafers with integrated and released sensitive micro- and nanosystems a fluxless wafer-level hermetic packaging solution is required. By using a 1.5 µm thick Sn layer as oxidation barrier for 5.0 µm thick Cu bond frames, the surface does not require pre-cleaning or use of any flux agent prior to, or during Cu-Sn bonding. With a tailored temperature and pressure bonding profile, the amount of Sn squeeze-out is reduced. Both for Cu-Sn bonds performed with new and aged electroplated films the measured shear strength is above 30 MPa. Further temperature cycling of bonded dies does not result in any reduction in bonding yield or shear strength.

A silicon sensor for measurement of liquid flow and thickness of fouling biofilms

Abstract A silicon sensor for the measurement of the flow velocity and thickness of a flouling biofilm was designed and fabricated. Using micro-machining in silicon, small and thermally-insulated sensor areas could be constructed. A physical model was worked out showing that with a double-chip method, both flow velocity and biofilm thickness can be measured. Experiments showed that this method gave a smaller accuracy in thickness measurements compared to a single-chip method at constant flow velocity. The accuracy in thickness measurement was ±0.5 for the single-chip method at ±3.5 μm for the double-chip method. The accuracy in flow velocity measurement decreased at increased film thickness, from about ±10% of the measured value at zero film thickness to about ±30% of the measured value at 20μm film thickness. A pilot experiment studying biofilm development in sea water over a period of 48 days is also presented.

CMOS-Integrated Si/SiGe Quantum-Well Infrared Microbolometer Focal Plane Arrays Manufactured With Very Large-Scale Heterogeneous 3-D Integration

We demonstrate infrared focal plane arrays utilizing monocrystalline silicon/silicon-germanium (Si/SiGe) quantum-well microbolometers that are heterogeneously integrated on top of CMOS-based electronic read-out integrated circuit substrates. The microbolometers are designed to detect light in the long wavelength infrared (LWIR) range from 8 to 14 μm and are arranged in focal plane arrays consisting of 384 × 288 microbolometer pixels with a pixel pitch of 25 μm × 25 μm. Focal plane arrays with two different microbolometer designs have been implemented. The first is a conventional single-layer microbolometer design and the second is an umbrella design in which the microbolometer legs are placed underneath the microbolometer membrane to achieve an improved pixel fill-factor. The infrared focal plane arrays are vacuum packaged using a CMOS compatible wafer bonding and sealing process. The demonstrated heterogeneous 3-D integration and packaging processes are implemented at wafer-level and enable independent optimization of the CMOS-based integrated circuits and the microbolometer materials. All manufacturing is done using standard semiconductor and MEMS processes, thus offering a generic approach for integrating CMOS-electronics with complex miniaturized transducer elements.

A model for the etch-stop location on reverse-biased pn junctions

Abstract This paper reports a model to predict where the silicon anisotropic electrochemical etching terminates on reverse-biased pn junctions. The model explains why the etching process terminates well before the metallurgical junction. The effects of the substrate doping, the type of junction (step or graded), the etching temperature and voltage bias, as well as the technique used (three and four electrodes) are analysed and compared with the experimental data. Some limitations and deviations from this theory are also pointed out.

Cu-Sn Wafer Level Bonding for Vacuum Encapsulation of Microbolometer Focal Plane Arrays

Wafer level packaging is the key to achieving cost efficiency and high reliability of the packaging of MEMS in high volume production. For many MEMS devices hermetic encapsulation in vacuum is required by their functionality, for example for high dynamic range or high sensitivity. In particular, for uncooled IR microbolometers vacuum packaging is critical for minimizing the heat loss by convection from the IR sensitive pixels to the gas residing in the package. As shown by calculations, at sufficiently low pressures the bolometer performance is not affected anymore by the surrounding pressure (below 1Pa for our device). In this paper a process for wafer-level hermetic vacuum encapsulation based on Cu-Sn SLID (solid-liquid interdiffusion) bonding is presented. It is being developed for Sensonor’s long-wave infrared bolometer, but it can also be used for vacuum encapsulation of other MEMS devices containing fragile or sensitive released structures. In the final product, one of the two wafers to be bonded contains the bolometer read out integrated CMOS circuit on which the IR sensitive pixels are integrated by post processing. These pixels are released by etching of a sacrificial oxide layer using anhydrous vapor HF. At this process step, the metal frames for the final encapsulation are already defined on the wafer. The cap wafer that seals the focal plane arrays contains a patterned thin film getter that will trap the residual gases in the bonded cavities and thereby ensures the required vacuum level for the entire life time of the device. The getter material is activated by a thermal annealing step, typically at 350°C. These particular characteristics of the active devices on the wafers impose certain restrictions to the process used for the final vacuum encapsulation step. The bonding temperature must be low enough to be compatible with the CMOS wafer as well as the pixel materials and structure, while at the same time the joint must resist the temperature of the subsequent getter activation. The bonding frames must withstand the etching of the sacrificial layer for the release of the pixels. Due to the presence of the released pixels, no wet chemical treatment of the wafers is allowed prior to bonding. Cu-Sn SLID bonding has been proven to fulfill the requirements related to the temperature and material compatibility, and we have developed a process that does not require pre-bonding cleaning of the metal surfaces. The bonding process relies on intermetallic compounds that form rapidly by interdiffusion of the two metallic layers, one with high (Cu) and one with low (Sn) melting points, when they are brought into intimate contact and at a temperature above the melting point of the latter. After bonding, the interface layer consists of the intermetallic phases Cu6Sn5 and Cu3Sn, the proportion of which depending on the initial ratio of the available Cu and Sn as well as the process temperature and time. By properly choosing the thicknesses of the initial Cu and Sn layers, and the process parameters, it is possible to raise the melting point of the final joint to a temperature significantly above the temperature of the bonding process. This offers the advantages of both low temperature bonding ( 400°C). Conventional Cu-Sn bonding has relied on a Cu-Sn layer stack on one side and a single Cu layer on the other. However, Cu layers that are exposed to ambient atmosphere oxidize easily, forming a barrier to Cu-Sn interdiffusion that inhibits intermetallic growth at the interface. A pre-bonding surface treatment is therefore required to remove any copper oxide from the top surface of the exposed Cu layer. Several wet chemical treatments are very effective for this purpose, but prohibited from the use on the wafer that contains the released pixels. The novelty of the process that we propose relies on the deposition of a Sn layer on both wafers, protecting the Cu layer underneath from oxidizing. The influence of different parameters on the bonding result has been investigated (process temperature and time, temperature at wafers contact, layout of the frames). Wafer level bonding of Cu/Sn to Cu/Sn layers with very good yield has been demonstrated. Figure 1 presents an IR picture of a 150mm wafer-pair bonded in vacuum. When exposed to atmospheric pressure, the two sides of the bonded cavities deflect towards each other (shown by the concentric interference fringes), confirming that the pressure in the cavities is very low. Further analysis of cross sections through the bonded frames reveals formation of Cu-Sn intermetallic layers as expected, as shown in Figure 2. In this example the bottom frame consists of four metal rails. It can be seen that in the regions where the top and bottom rails overlap, all of the Sn has reacted with Cu and formed Cu3Sn. The intermetallic compound between the rails is Cu6Sn5. The strength of the joints was measured using a shear test, which resulted in an average value of 35MPa. No significant change in shear strength was observed after thermal cycling (1000 cycles, -40°C/150°C). Comparing the caps deflection for vacuum bonded dies before and after annealing at 350°C (simulating the process of the getter activation) have not revealed any significant changes. Nor has any obvious change of the intermetallic structure been observed either.

Low cost, high performance far infrared microbolometer

Far infrared (FIR) is becoming more widely accepted within the automotive industry as a powerful sensor to detect Vulnerable Road Users like pedestrians and bicyclist as well as animals. The main focus of FIR system development lies in reducing the cost of their components, and this will involve optimizing all aspects of the system. Decreased pixel size, improved 3D process integration technologies and improved manufacturing yields will produce the necessary cost reduction on the sensor to enable high market penetration. The improved 3D process integration allows a higher fill factor and improved transmission/absorption properties. Together with the high Thermal Coefficient of Resistance (TCR) and low 1/f noise properties provided by monocrystalline silicon germanium SiGe thermistor material, they lead to bolometer performances beyond those of existing devices. The thermistor material is deposited and optimized on an IR wafer separated from the read-out integrated circuit (ROIC) wafer. The IR wafer is transferred to the ROIC using CMOS compatible processes and materials, utilizing a low temperature wafer bonding process. Long term vacuum sealing obtained by wafer scale packaging enables further cost reductions and improved quality. The approach allows independent optimization of ROIC and thermistor material processing and is compatible with existing MEMS-foundries, allowing fast time to market.