Glen D. Wilk

Hafnium and zirconium silicates for advanced gate dielectrics

Hafnium and zirconium silicate (HfSixOy and ZrSixOy, respectively) gate dielectric films with metal contents ranging from ∼3 to 30 at.u200a% Hf, or 2 to 27 at.u200a% Zr (±1 at.u200a% for Hf and Zr, respectively, within a given film), have been investigated, and films with ∼2–8 at.u200a% Hf or Zr exhibit excellent electrical properties and high thermal stability in direct contact with Si. Capacitance–voltage measurements show an equivalent oxide thickness tox of about 18 A (21 A) for a 50 A HfSixOy (50 A ZrSixOy) film deposited directly on a Si substrate. Current–voltage measurements show for the same films a leakage current of less than 2×10−6u200aA/cm2 at 1.0 V bias. Hysteresis in these films is measured to be less than 10 mV, the breakdown field is measured to be EBD∼10u200aMV/cm, and the midgap interface state density is estimated to be Dit∼1–5×1011u200acm−2u200aeV−1. Au electrodes produce excellent electrical properties, while Al electrodes produce very good electrical results, but also react with the silicates, creating a lower e l...

Electrical properties of hafnium silicate gate dielectrics deposited directly on silicon

Hafnium silicate (HfSixOy) gate dielectric films with ∼6 at.u200a% Hf exhibit significantly improved leakage properties over SiO2 in the ultrathin regime while remaining thermally stable in direct contact with Si. Capacitance–voltage measurements show an equivalent oxide thickness (tox) of less than 18 A for a 50 A HfSixOy film deposited directly on a Si substrate, with no significant dispersion of the capacitance for frequencies ranging from 10 kHz to 1 MHz. Current–voltage measurements show for the same film a leakage current of 1.2×10−6u200aA/cm2 at 1 V bias. Hysteresis in these films is measured to be less than 20 mV, the breakdown field is measured to be EBD∼10u200aMV/cm, and the midgap interface state density is Dit∼1011u200acm−2u200aeV−1. Cross-sectional transmission electron microscopy shows no signs of reaction or crystallization in HfSixOy films on Si after being annealed at 800u200a°C for 30 min.

Stable zirconium silicate gate dielectrics deposited directly on silicon

Zirconium silicate (ZrSixOy) gate dielectric films with ∼3–5 at.u200a% Zr exhibit excellent electrical properties and high thermal stability in direct contact with Si. We demonstrate an equivalent oxide thickness of about 21 A for a 50 A ZrSixOy film sputter-deposited directly on a Si substrate, as measured by capacitance–voltage techniques, with a hysteresis shift less than 10 mV. Leakage currents for these films are very low, approximately 1×10−6 A/cm2 at 1.0 V bias in accumulation. Films ramped to hard breakdown exhibit breakdown fields Ebd ∼10 MV/cm. Excellent electrical properties are obtained with Au electrodes, in particular.Zirconium silicate (ZrSixOy) gate dielectric films with ∼3–5 at.u200a% Zr exhibit excellent electrical properties and high thermal stability in direct contact with Si. We demonstrate an equivalent oxide thickness of about 21 A for a 50 A ZrSixOy film sputter-deposited directly on a Si substrate, as measured by capacitance–voltage techniques, with a hysteresis shift less than 10 mV. Leakage currents for these films are very low, approximately 1×10−6 A/cm2 at 1.0 V bias in accumulation. Films ramped to hard breakdown exhibit breakdown fields Ebd ∼10 MV/cm. Excellent electrical properties are obtained with Au electrodes, in particular.

Direct extraction of the electron tunneling effective mass in ultrathin SiO2

Electron transport in ultrathin (tox<40 A) Al/SiO2/n−Si structures is dominated by direct tunneling of electrons across the SiO2 barrier. By analyzing the tunneling currents as a function of the SiO2 layer thickness for a comprehensive set of otherwise identical samples, we are able to extract an effective mass for the tunneling electron in the SiO2 layer. Oxide films 16–35 A thick were thermally grown in situ in a dry oxygen ambient. The oxide thicknesses were determined by capacitance–voltage measurements and by spectroscopic ellipsometry. The tunneling effective mass was extracted from the thickness dependence of the direct tunneling current between an applied voltage of 0 and 2 V, a bias range that has not been previously explored. Employing both a parabolic and a nonparabolic assumption of the E−κ relationship in the oxide forbidden gap, we found the SiO2 electron mass to be mP*=0.30±0.02me, and mNP*=0.41±0.01me, respectively, independent of bias. Because this method is based on a large sample set, t...

SiO2 film thickness metrology by x-ray photoelectron spectroscopy

Silicon dioxide films grown by industrial thermal furnace, rapid thermal, and low-pressure thermal methods were measured by x-ray photoelectron spectroscopy, transmission electron microscopy (TEM), spectroscopic ellipsometry, and capacitance–voltage analysis. Based on TEM measurements, the photoelectron effective attenuation lengths in the SiO2 and Si are found to be 2.96±0.19 and 2.11±0.13u2009nm, respectively. The oxide physical thicknesses (range from 1.5 to 12.5 nm) as measured by all above techniques are in good agreement. The electrical thickness is noted to be slightly thicker than the physical thickness.

In situ Si flux cleaning technique for producing atomically flat Si(100) surfaces at low temperature

We have developed a method for removing oxides and producing atomically flat Si(100) surfaces with single atomic height steps using a Si flux cleaning technique. By introducing a Si flux in the range 1.0–1.5 A/s at the onset of an SiO2 thermal desorption step as low as 780u2009°C, scanning tunneling microscopy (STM) and atomic force microscopy images reveal smooth surfaces with atomically flat terraces with an rms roughness of 0.5 A and single-step heights of 1.4 A. STM reveals that A- and B-type steps are present across the entire area of the scanned surface. Desorption of the surface oxide layer with Si fluxes below this range results in rougher surfaces with pits ∼50 A deep and 1000 A across. For Si fluxes above this range, no pits are seen but atomic steps are not visible on the surface.

Surface preparation, growth, and characterization of ultrathin gate oxides for scaled CMOS applications

CMOS scaling is requiring increased attention on several aspects of ultrathin oxides, including both physical and electrical properties. In particular, surface preparation and interface quality will play an increasingly important role as the gate oxide thickness is scaled down to below 30 angstroms for sub-0.1 micrometer devices. This means that standard thermal desorption of sacrificial oxides or even H-terminated surfaces will have to be closely investigated to determine if the requirements for interface roughness and uniformity can still be met, or whether new preparation techniques will have to be used. Growth of oxides in the ultrathin regime is also a concern because of uniformity and reproducibility problems using furnaces, including pinhole formation in films. Physical and electrical characterization of ultrathin oxides presents difficulties with most currently used techniques. Measurement of the oxide thickness below 30 angstrom involves substantial uncertainties in standard techniques such as spectroscopic ellipsometry form impurities and interface roughness and in C- V analysis from large tunneling currents and poly-depletion effects. One possibility for overcoming these problems is to use the direct tunneling current to determine the electrical thickness of the oxides. It is important to characterize the effect of decreasing oxide thickness in the ultrathin regime on fundamental parameters such as the electron effective mass m* and the band gap, especially for predicting the electrical behavior of these oxides. Boron penetration effects also present problems for device operation with the ultrathin oxides which need to be addressed. The combination of these concerns leads toward alternate gate dielectric materials with higher dielectric constants and higher resistance to B diffusion.

Beyond-The-Roadmap Technology: Silicon Heterojunctions, Optoelectronics, and Quantum Devices

The roadmap for silicon device technology has been drawn, extending to the year 2010, and featuring a CMOS transistor with a gate length of 0.07 μm [1]. Beyond this point, silicon heterojunctions could provide a means to further device scaling. Silicon heterojunctions could also bring new devices to the silicon substrate including light emitters and detectors, and resonant tunneling diodes (RTDs). Today SiGe/Si and SiGeC/Si heterojunctions are receiving the greatest attention, but heterojunctions now being developed to realize silicon RTDs are increasing the heterojunction options for silicon-based quantum-well and optical devices. Here we outline the fundamental device requirements for silicon optical and tunneling devices and describe progress on silicon heterojunction development towards demonstration of silicon-based RTDs. Materials now under study include, ZnS, crystalline oxides and nitrides; new processes could provide methods for forming crystalline materials over amorphous barriers.

Low temperature chemical vapor deposition of titanium dioxide thin films using tetranitratotitanium (IV)

Crystalline titanium dioxide films were deposited on silicon (100) at temperatures as low as 184°C using the volatile molecular precursor, tetranitratotitanium(IV). Deposition rates in a low pressure chemical vapor deposition (LPCVD) reactor operated at 230 – 500°C with a precursor vessel temperature at 22°C were typically 4 nm/min. The effect of deposition temperature and annealing conditions on morphology are shown. Following post-deposition annealing in oxygen and hydrogen, Pt/TiO 2 /Si/Al capacitors were fabricated and exhibited dielectric constants in the range of 19 – 30 and leakage current densities as low as 10 −8 Amp/cm 2 .