David C. Gilmer

Titanium dioxide (TiO 2 )-based gate insulators

Titanium dioxide has been deposited on silicon for use as a high-permittivity gate insulator in an effort to produce low-leakage films with oxide equivalent thicknesses below 2.0 nm. Excellent electrical characteristics can be achieved, but TEM and electrical measurements have shown the presence of a low-resistivity interfacial layer that we take to be SiO2. The leakage current follows several mechanisms depending on the bias voltage. Reasonably good agreement has been seen between current-voltage measurements and a 1D quantum transport model.

Fermi-level pinning at the polysilicon/metal-oxide interface-Part II

We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the different gatestack regions and determined that the polysilicon/metal oxide interface plays a key role on the threshold voltages. Now in Part II, the effects of the interfacial bonding are examined by experiments with submonolayer atomic-layer deposition (ALD) metal oxides and atomistic simulation. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. Oxygen vacancies at polysilicon/HfO/sub 2/ interfaces also lead to Fermi pinning. This fundamental characteristic affects the observed polysilicon depletion.

Fermi level pinning at the polySi/metal oxide interface

We report here for the first time that Fermi pinning at the polySi/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. This fundamental characteristic also affects the observed polySi depletion. Device data and simulation results will be presented.

Challenges for the integration of metal gate electrodes

Integration challenges for metal gate electrodes including the presence of Fermi level pinning and the impact of interface chemistry on the effective metal work function are discussed. Gate stack thermal instabilities are explored, and for the first time results using tantalum-carbon based electrodes are presented.

Compatibility of polycrystalline silicon gate deposition with HfO2 and Al2O3/HfO2 gate dielectrics

Polycrystalline-silicon (poly-Si) gate compatibility issues with HfO2 and Al2O3 capped HfO2 gate dielectrics are reported. It can be generally stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto HfO2 results in electrical properties much worse compared to similar HfO2 films using platinum metal gates. However, depositing CVD silicon gates directly onto Al2O3 capped HfO2 showed greater than a 104 times reduction in gate leakage compared to the poly-Si/HfO2 and poly-Si/SiO2 controls of similar electrical thickness.

Dual-metal gate CMOS with HfO 2 gate dielectric

We report for the first time on a novel dual-metal gate CMOS integration on HfO/sub 2/ gate dielectric using TiN (PMOS) and TaSiN (NMOS) gate electrodes. Compared to a single metal integration, the dual-metal integration does not degrade gate leakage, mobility and charge trapping behavior. Promising preliminary TDDB data were obtained from dual-metal gate MOSFETs, while still delivering much improved gate leakage (10/sup 4/ - 10/sup 5/ X better than SiO/sub 2/).

Tantalum carbonitride electrodes and the impact of interface chemistry on device characteristics

The intent of this research is to understand the role of interface chemistry on the effective work function and device characteristics of metal gate electrodes on hafnium dioxide (HfO2) gate dielectrics in metal oxide semiconductor field effect transistors. Since multiple factors, including crystal structure, preferred orientation, chemical composition, interface bonding, and reactions or interdiffusions, impact the effective work function, solid-solution carbonitrides of tantalum (TaCxN1−x) have been studied in an attempt to isolate the role of interface chemistry on the effective work function. Tantalum carbonitride films have been carefully deposited with similar Ta∕(C+N) ratios to understand how the substitution of N for C on the octahedral interstice in a face-centered-cubic tantalum lattice impacts device performance. Results indicate that the effective work function and device threshold voltage are reduced when the less electronegative carbon atom is substituted for the more electronegative nitroge...

Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/HfO/sub 2/ stack

Threshold voltage instability is a critical problem for high-K dielectric implementation. This problem is much more serious for short channel devices due to process induced gate edge damage. A novel stress relieved pre-oxide (SRPO) followed by ALD of HfO/sub 2/ reduces the local charge density near the gate edge and short channel threshold voltage instability. Excellent cross wafer CETinv uniformity is achieved for the SRPO process. A new tantalum carbon alloy metal gate achieves a lower Vtsat than TaSiN gated devices due to a lower work function. Compared to HfO/sub 2//TaSiN devices using standard RCA pre-clean, HfO/sub 2//tantalum carbon alloy metal gate stack using the novel SRPO demonstrates a 3/spl times/ smaller Vt shift for short channel devices and a 16% Ion/Ioff improvement.

80 nm poly-Si gate CMOS with HfO/sub 2/ gate dielectric

We report here for the first time the formation of an amorphous oxide layer between the polysilicon gate and hafnium oxide (HfO/sub 2/) gate dielectric due to a lateral oxidation mechanism at the gate edge. Using a polySi reoxidation-free CMOS process, well behaved 80 nm MOSFETs were fabricated with no evidence of lateral oxidation. A CETinv of 25 /spl Aring/ with a leakage current 1000/spl times/ lower than SiO/sub 2/ was obtained for a 30 /spl Aring/ HfO/sub 2//12 /spl Aring/ interfacial oxide stack. In this paper, we present results on the physical and electrical characterization.

Atomic layer deposition of HfO2 thin films and nanolayered HfO2–Al2O3–Nb2O5 dielectrics

Smooth, 4–6-nm thick hafnium oxide films were grown by atomic layer deposition from HfI4 or HfCl4 and H2O on SiO2/Si(1 0 0) substrates at 300 °C. Non-uniform films were obtained on hydrogen-terminated Si(1 0 0). The stoichiometry of the films corresponded to that of HfO2. The films contained small amounts of residual chlorine and iodine. The films deposited on SiO2/Si(1 0 0) were amorphous, but crystallized upon annealing at 1000 °C. In order to decrease the conductivity, the HfO2 films were mixed with Al2O3, and to increase the capacitance, the films were mixed with Nb2O5. The capacitance–voltage curves of the Hf–Al–O mixture films showed hysteresis. The capacitance–voltage curves of HfO2 films and mixtures of Hf–Al–Nb–O were hysteresis free.