Gopi Ganapathy

Hardware emulation for functional verification of K5

The K5 microprocessor is a 4 Million transistor superscalar, X86 microprocessor. The K5 microprocessor is an AMD original design, verifying compatibility with the existing X86 architecture and software is crucial to its success in the market place. The X86 architecture has been constantly evolving over several years without any published specification. The primary mechanism for functional design verification of an X86 processor is simulation. The ability to execute a good sample set of the X86 software base on a model of the processor architecture before tapeout is key to achieving very high confidence first silicon. The Quickturn Hardware Emulation system allows us to map a model of the design onto hardware resources and execute it at high speeds. In this paper we present the emulation methodology that was jointly developed for K5 and applied successfully to meet our functional verification goals.

HARDWARE ACCELERATION ALONE WILL NOT MAKE FAULT GRADING ULSI A REALITY

A low cost deterministic fault simulation technique for practical ultra large scale integrated WSI) circuits, in a hardware accelerator environment is presented. A dynamic test directed partitioning scheme is implemented to select the faults which should be deterministically simulated for a given pattern. Experimental data show a speedup greater than an order of magnitude over conventionad fault simulation.

Selective Pseudo Scan - Combinational Atpg with Reduced Scan in a Full Custom Risc Microprocessor

This paper presents a novel test generation technique, called Selective Pseudo Scan (SPS), which incurs very low overhead. SPS uses a commercial combinational ATPG tool to generate tests with high fault coverage by reconfiguring sequential circuits to appear combinational without inserting scan. Results of applying SPS to several complex control blocks of a full custom RISC Microprocessor, demonstrate its superiority compared to traditional full scan or partial scan in a full custom design environment.