Goran Bilski

Designing Soft Processors for FPGAs

Publisher Summary This chapter shows the implementation of architectural elements, such as buses, muxes, ALUs, register files, and FIFOs on FPGAs, and the tradeoffs involved in selecting different size parameters for these architectural elements. The architecture of the soft processor is constrained by the FPGA implementation fabric. For example, the number of pipe stages is limited to three in our example, because adding more pipe stages increases the number and the size of multiplexers in the processor, and the relatively high cost of these multiplexers (relative to ASIC implementations) reduces the possible speed advantage. However, these relative costs can change as the FPGA fabric evolves, and new optimizations might be necessary. The speed and area of these implementations dictate whether a bus-based or mux-based processor implementation is chosen. The use of lookup tables (LUTs) instead of logic gates implies that some additional logic is free, but beyond a certain point there is variation in terms of the speed/area of an implementation.