Gordon J. Brebner

Universal schemes for parallel communication

In this paper we isolate a combinatorial problem that, we believe, lies at the heart of this question and provide some encouragingly positive solutions to it. We show that there exists an N-processor <underline>realistic</underline> computer that can simulate arbitrary <underline>idealistic</underline> N-processor parallel computations with only a factor of O(log N) loss of runtime efficiency. The main innovation is an O(log N) time randomized routing algorithm. Previous approaches were based on sorting or permutation networks, and implied loss factors of order at least (log N)<supscrpt>2</supscrpt>.

A Virtual Hardware Operating System for the Xilinx XC6200

Computer operating systems relieve a user of the responsibility for managing physical resources, such as processors, memory and input/output devices. The evolution of FPGA technology means that a new resource is available — it is accessed like memory, but can behave like a flexible processor or input/output device. There is a role for an operating system in making this resource easy to use, by managing it on behalf of a user. This paper explores the issues involved in such management, in particular the problems involved in presenting a software-oriented user with a larger virtual hardware resource that is implemented using smaller physical FPGA hardware. A prototype operating system, that demonstrates operational solutions to the problems using the Xilinx XC6200 FPGA, is described.

OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems

This paper presents the OpenDF framework and recalls that dataflow programming was once invented to address the problem of parallel computing. We discuss the problems with an imperative style, von Neumann programs, and present what we believe are the advantages of using a dataflow programming model. The CAL actor language is briefly presented and its role in the ISO/MPEG standard is discussed. The Dataflow Interchange Format (DIF) and related tools can be used for analysis of actors and networks, demonstrating the advantages of a dataflow approach. Finally, an overview of a case study implementing an MPEG- 4 decoder is given.

Chip-Based Reconfigurable Task Management

Modularity is a key aspect of system design, particularly in the era of system-on-chip. Field-programmable logic (FPL), particularly with the rapid increase in programmable gate counts, is a natural medium to host run-time modularity, that is, a dynamically-varying ensemble of circuit modules. Prior research has presumed the use of an external processor to manage such an ensemble. In this paper, we consider on-chip management, implemented in the FPL itself, based upon a one-dimensional allocation model. We demonstrate an algorithm for on-chip identification of free FPL resource for modules, and an approach to on-chip rearrangement of modules. The latter includes a proposal for a realistic augmentation to existing FPGA reconfiguration architectures. The work represents a key demonstration of how FPL can be used as a first-order computational resource, rather than just as a slave to the microprocessor.

400 Gb/s Programmable Packet Parsing on a Single FPGA

Packet parsing is necessary at all points in the modern networking infrastructure, to support packet classification and security functions, as well as for protocol implementation. Increasingly high line rates call for advanced hardware packet processing solutions, while increasing rates of change call for high-level programmability of these solutions. This paper presents an approach for harnessing modern Field Programmable Gate Array (FPGA) devices, which are a natural technology for implementing the necessary high-speed programmable packet processing. The paper introduces PP: a simple high-level language for describing packet parsing algorithms in an implementation-independent manner. It demonstrates that this language can be compiled to give high-speed FPGA-based packet parsers that can be integrated alongside other packet processing components to build network nodes. Compilation involves generating virtual processing architectures tailored to specific packet parsing requirements. Scalability of these architectures allows parsing at line rates from 1 to 400 Gb/s as required in different network contexts. Run-time programmability of these architectures allows dynamic updating of parsing algorithms during operation in the field. Implementation results show that programmable packet parsing of 600 million small packets per second can be supported on a single Xilinx Virtex-7 FPGA device handling a 400 Gb/s line rate.

Networking on chip with platform FPGAs

This paper is concerned with networking at the chip level. Networks on chip have become a convenient focus for discussing the architecture of systems on chip, and design methodologies for such systems. One central question for such a focus concerns the extent to which it is useful or realistic just to scale down approaches used conventionally in larger-area computer networking. Here, we discuss this question, in the context of the modern Platform FPGA device as a system on chip substrate. We illustrate the discussion with two design examples of networking on chip being implemented in an unconventional way.

Mapping a domain specific language to a platform FPGA

A domain specific language (DSL) enables designers to rapidly specify and implement systems for a particular domain, yielding designs that are easy to understand, reason about, re-use and maintain. However, there is usually a significant overhead in the required infrastructure to map such a DSL on to a programmable logic device. In this paper, we present a mapping of an existing DSL for the networking domain on to a platform FPGA by embedding the DSL into an existing language infrastructure. In particular, we will show that, using few basic concepts, we are able to achieve a successful mapping of the DSL on to a platform FPGA and create a re-usable structure that also makes it easy to extend the DSL. Finally we will present some results of mapping the DSL on to a platform FPGA and comment on the resulting overhead.

Single-chip gigabit mixed-version IP router on Virtex-II Pro

This paper concerns novel single-chip system architecture options, based on the Xilinx Virtex-II Pro part, which includes up to four PowerPC cores and was launched in Spring 2002. The research described here was carried out pre-launch (i.e., prior to availability of real parts), so the paper focuses on initial architectural experiments based on simulation. The application is a Mixed-version IP Router, named MIR, servicing gigabit ethernet ports. This would be of use to organizations with several gigabit ethernets, with a mixture of IPv4 and IPv6 hosts and routers attached directly to the networks. A particular benefit of a programmable approach based on Virtex-II Pro is that the routers functions can evolve smoothly, maintaining router performance as the organization migrates from IPv4 to IPv6 internally, and also as the Internet migrates externally. The basic aim is to carry out more frequent, and less control intensive, functions in logic, and other functions in the processor. Two prototypes are described here. Both support four ethernet ports, but the designs are scalable upwards. The second one, the more ambitious of the two, instantiates a configuration appropriate when the bulk of the incoming packets are IPv4. Such packets are processed and switched entirely by logic, with no internal copying of packets between buffers and virtually no delay between packet receipt and onward forwarding. This involves a specially-tailored internal interconnection network between the four ports, and also processing performed in parallel with packet receipt, i.e. multi-threading in logic. IPv6 packets, or some rare IPv4 cases, are passed to a PowerPC core for processing. In essence, the PowerPC acts as a slave to the logic, rather than the more common opposite master-slave relationship.

High-Speed Packet Processing using Reconfigurable Computing

Internet applications, notably streaming video, demand extremely high communication speeds in core networks, currently 100 Gbps and moving toward 400 Gbps and beyond. Data packets must be processed at these rates, presenting serious challenges for traditional computing approaches. This article presents a tool chain that maps a domain-specific packet-processing language called PX to high-performance reconfigurable-computing architectures based on field-programmable gate array (FPGA) technology. PX is a declarative language with object-oriented semantics. A customized computing architecture is generated to match the exact requirements expressed in the PX description. The architecture includes components for packet parsing and editing, and for table lookups. It is expressed in a register transfer level (RTL) description, which is then processed using standard FPGA implementation tools. The architecture is dynamically programmable via custom firmware updates when the packet-processing system is in operation. The authors illustrate the language, tool chain, and implementation results through a practical example involving a 100-Gbps OpenFlow implementation.

Runtime reconfigurable routing

This paper is concerned with practicable solutions to a dynamic circuit reconfiguration problem: how to perform runtime routing of data between blocks of circuitry. The solutions use a ‘virtual circuitry’ approach based on the notion of Swappable Logic Units (SLUs). They involve a continuum of three types of routing model in which communication channels are made available using some form of extra configured logic supplied by an operating system. These models involve trade-offs between flexibility, speed and cell count; however, all stop short of any impractical attempt at arbitrary routing at run time. The models also illustrate a blurring of traditional notions of ‘hardware’ and ‘software’, at a point where circuitry meets instruction sequences.