Philip B. James-Roxby

A Self-reconfiguring Platform

A self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. This platform has been implemented on Xilinx Virtex II tm and Virtex II Pro tm devices. The platform’s hardware architecture has been designed to be lightweight. Two APIs (Application Program Interface) are described which abstract the low level configuration interface. The Xilinx Partial Reconfiguration Toolkit (XPART), the higher level of the two APIs, provides methods for reading and modifying select FPGA resources. It also provides support for relocatable partial bitstreams. The presented self-reconfiguring platform enables embedded applications to take advantage of dynamic partial reconfiguration without requiring external circuitry.

Lava and JBits: From HDL to Bitstream in Seconds

The paper reports a design methodology that allows FPGA programming bitstreams to be generated in seconds starting from a very high level circuit description. High speed bitstream generation and manipulation is particularly important for reconfigurable computing systems that can not wait for the typical run times incurred by conventional flows. The preliminary version of this system can generate bitstreams from HDL source 12 times faster than the conventional flow and future work may offer significantly larger speed improvements.

An Efficient Content-Addressable Memory Implementation Using Dynamic Routing

Content addressable memories are important components in high-speed networking equipment. This paper describes the design of a wide CAM suitable for use as an IPv6 traffic classifier for a 622Mb/s communications link. The design flow uses a combination of standard design tools in conjunction with JBits, a low-level configuration API for manipulating programmable resources. The CAMs are 320 bits wide to accommodate a full IPv6 header. The most powerful wildcarding possible is supported, ranging from don’t cares on single bits of the header, all the way through to don’t cares for the whole header. A priority mechanism has been designed which allows explicit priority encoding to be used without required a costly sorting network. This is performed by dynamic routing, whereby routes are determined at run-time between the match units and the priority encoder. This allows a smaller, faster implicit priority encoder to be used, whilst still allowing priority to be explicitly defined. An experimental set-up is shown, which allows 128 320-bit patterns to be matched at 50.9 Msearches/s.

Hyper-programmable architectures for adaptable networked systems

We explain how modern programmable logic devices have capabilities that are well suited for them to assume a central role in the implementation of networked systems, now and in the future. To date, such devices have featured largely in ASIC substitution roles within networked systems; this usage has been highly successful, allowing faster times to market and reduced engineering costs. We argue that there are many additional opportunities for productively using these devices. The requirement is exposure of their high inherent computational concurrency matched by concurrent memory accessibility, their rich on-chip interconnectivity and their complete programmability, at a higher level of abstraction that matches the implementation needs of networked systems. We discuss specific examples supporting this view, and present a highly flexible soft platform architecture at an appropriate level of abstraction from physical devices. This may be viewed as a particularly configurable and programmable type of network processor, offering scope both for innovative networked system implementation and for new directions in networking research. In particular, it is aimed at facilitating scalable solutions, matching differently resourced programmable logic devices to differing performance and sophistication requirements of networked systems, from cheap consumer appliances to high-end network switching.

Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits

A technique for rapidly generating configuration datastreams from high-level HDL-like constructs is introduced. This new technique allows a wide variety of client applications to send a fully placed netlist to a sever which routes the netlist and then generates a configuration datastream (either full or partial). The configuration datastream can then be used by the client to reconfigure hardware. This new technology provides an experimental infrastructure that can realize many existing abstractions for reconfigurable computing. This paper considers an implementation of configuration data graphs.

Designing application -specific cores using JBits: A run-time parameterizable FIR filter

An example of an application-specific core is described, which embodies domain specific knowledge in with the construction of parameterizable circuit. Application-specific cores present a more familiar interface to the end user, since parameters are now domain-specific rather than core-specific. A FIR filter is described, which is parameterizable at run-time by its desired frequency response. The core can calculate its own weights, and a configuration datastream suitable for downloading to a programmable device in a matter of seconds, opening up a new realm of testing, both at the core level and at the system level.

Multithreading in a Hyper-programmable Platform for Networked Systems

Modern programmable logic devices have capabilities that are well suited for them to assume a central role in the implementation of networked systems. We have devised a highly flexible soft platform architecture abstracted from such physical devices, which may be viewed as a particularly configurable and programmable type of network processor. In this paper, we discuss multithreading in the context of this logic-centric soft platform, and describe the programmable mechanisms to support multithreading that we have implemented. Through a design example, we evaluate these mechanisms, and report that the solution obtained had comparable performance to a custom solution written from scratch without the intermediate soft platform.

High-performance reconfigurable constant coefficient multiplier implementations

The use of dynamic reconfiguration appears extremely attractive for implementing adaptive processing algorithms. Often, the adaption involves updating look-up tables based on a parameter which can only be determined at run-time. For reasons of efficiency, these look-up tables are read-only to the rest of the circuitry. This paper compares the use of run-time reconfiguration and read-only look-up tables, with similar implementations using writable memories. The application under consideration is the multi-layer perceptron neural network. It is shown that the ROM based network is considerably simpler than the RAM based network, at the expense of a dramatically increased time to update the weights during training.