Goro Hayakawa

Semiconductor integrated circuit having test circuit

Dynamic semiconductor memory device that can control through current of input buffer circuit for external input/output control signal

Semiconductor device having shared sense amplifier configuration

Semiconductor integrated circuit capable of readily adjusting circuit characteristic

Integrated semiconductor device

Semiconductor memory device capable of normal transition to test mode

Semiconductor memory device preventing malfunction during refresh operation even when noise is superimposed on control signal

Semiconductor memory e.g. DRAM has control circuit which activates/deactivates memory row, in response to read/write and refreshing modes

Tri-mode semiconductor DRAM appts. with CMOS buffer circuit

Dynamische Halbleiterspeichereinrichtung, in der drei Betriebsmoden festlegbar sind Dynamic semiconductor memory device in which three operating modes are fixed