Yasuhiko Tsukikawa

Semiconductor memory device having a redundant row and a redundant column which can be accessed prior to substitution

Charge pump circuit having an improved charge pumping efficiency

Synchronous semiconductor device having circuitry capable of surely resetting test mode

Semiconductor memory device capable of executing earlier command operation in test mode

Complementary differential amplifier in which direct current amplification gain can be set arbitrarily and semiconductor memory divice using the same

Semiconductor memory device having storage capacity of 22N+1 bits

Semiconductor memory device having test mode

Substrate potential generation circuit that can suppress variation of output voltage with respect to change in external power supply voltage and environment temperature

Semiconductor memory device and test method therefor

Semiconductor memory device clamping the overshoot and undershoot of input signal by circuit with PN junction