Goro Kitsukawa

Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs)

Analytical expressions are presented for subthreshold current reduction in a decoded-driver by self-reverse biasing, which is inherently required for low-voltage, low-power, high-speed DRAMs for portable equipment. The scheme involves inserting a switching MOS transistor between the driver circuits and its power supply line. The subthreshold current of the decoded-driver is reduced to the order of 10/sup -3/ in the practical temperature range (250-350 K) with 254 mV of self-reverse biasing voltage, while the delay time is only 3% more than in conventional schemes. The transition time of 1 ms from the operating state to the low subthreshold current state is sufficient to reduce the subthreshold current. The rapid recovery time of 1 ns from the low subthreshold current state does not interrupt the start of normal operation. The subthreshold current reduction was confirmed experimentally using a test chip fabricated with 0.25- mu m technology. >

A 23-ns 1-Mb BiCMOS DRAM

A 1-Mb BiCMOS DRAM having a 23-ns access time is described. The DRAM uses a direct sensing technique and a nonaddress-multiplexing configuration. This technique combines the NMOS differential circuit on each pair of data lines with a common highly sensitive bipolar circuit. The resulting chip has been verified to have high-speed characteristics while maintaining a wide operating margin and a relatively small chip size of 62.2 mm/sup 2/, in spite of a 1.3- mu m lithography level. >

256-Mb DRAM circuit technologies for file applications

256-Mb DRAM circuit technologies characterized by low power and high fabrication yield for file applications are described. The newly proposed and developed circuits are a self-reverse-biasing circuit for word drivers and decoders to suppress the subthreshold current to 3% of the conventional scheme, and a subarray-replacement redundancy technique that doubles chip yield and consequently reduces manufacturing costs. An experimental 256-Mb DRAM has been designed and fabricated by combining the proposed circuit techniques and a 0.25- mu m phase-shift optical lithography, and its basic operations are verified. A 0.72- mu m/sup 2/ double-cylindrical recessed stacked-capacitor (RSTC) cell is used to ensure a storage capacitance of 25 fF/cell. A typical access time under a 2-V power supply voltage was 70 ns. With the proper device characteristics, the simulated performances of the 256-Mb DRAM operating with a 1.5-V power supply voltage are a data-retention current of 53 mu A and an access time of 48 ns. >

A 29-ns 64-Mb DRAM with hierarchical array architecture

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-/spl mu/m CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71/spl times/1.20 /spl mu/m/sup 2/, and the chip size is 15.91/spl times/9.06 mm/sup 2/. A typical access time under 3.3 V power supply voltage is 29 ns.

256 Mb DRAM technologies for file applications

The authors describe 256-Mb DRAM (dynamic random access memory) technologies for file applications. A subthreshold-current limiting scheme for word drivers is shown. The scheme uses a pMOS switching transistor between the wordline voltage and the driver transistor common-source terminal. The subthreshold current of a 256-Mb DRAM is reduced to 3% by applying this scheme to word drivers and decoders, and the total data-retention current is less than that of a 64-Mb DRAM. A redundancy technique is shown which features subarray-by-subarray replacement instead of the conventional line-by-line replacement. To evaluate the circuit technologies described here, an experimental 256-Mb DRAM was fabricated using 0.25- mu m CMOS technology with phase-shift lithography. It uses a 0.72- mu m/sup 2/ RSTC cell with a storage capacitance of 25 fF and operates on a voltage of 1.5-3.6 V.<<ETX>>

A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques

A temperature-compensation circuit technique for a dynamic random-access memory (DRAM) with an on-chip voltage limiter is evaluated using a 1-Mb BiCMOS DRAM. It was found that a BiCMOS bandgap reference generator scheme yields an internal voltage immune from temperature and V/sub cc/ variation. Also, bipolar-transistor-oriented memory circuits, such as a static BiCMOS word driver, improve delay time at high temperatures. Furthermore, the BiCMOS driver proves to have better temperature characteristics than the CMOS driver. Finally, a 1-Mb BiCMOS DRAM using the proposed technique was found to have better temperature characteristics than the 1-Mb CMOS DRAM which uses similar techniques, as was expected. Thus, BiCMOS DRAMs have improved access time at high temperatures compared with CMOS DRAMs. >

An experimental 1-Mbit BiCMOS DRAM

Three developments are proposed for high-performance DRAMs: a bipolar complementary MOS (BiCMOS) DRAM device structure featuring high soft-error immunity due to a p/SUP +/ buried layer; a high-speed circuit configuration of eight NMOS subarrays combined with BiCMOS peripheral drivers and BiCMOS data output circuitry; and BiCMOS voltage and current limiters lowering power dissipation as well as peak current. A 1.3 /spl mu/m 1-Mb DRAM is designed and fabricated to verify the usefulness of these BiCMOS DRAM technologies. Features of this chip include a typical access time of 32 ns, a typical power dissipation of 450 mW at a 60-ns cycle time, and chip size of 5.0/spl times/14.9 mm/SUP 2/.

A charge recycle refresh for Gb-scale DRAM's in file applications

A charge recycle refresh for low-power DRAM data-retention, featuring alternative operation of two memory arrays, is proposed, and demonstrated using a 64 kb test chip with 0.25 /spl mu/m technology. After amplification in one array, the charges in that array are transferred to another array, where they are recycled for half amplification. The data-line current dissipation is only half that of the conventional refresh operation, and the voltage bounce of the power supply line is 60% of the conventional. This scheme is further extended for application to n arrays with 1/n data-line current dissipation. Moreover, the multi-array activation with charge recycle refresh is proposed, in which the same peak current as in the conventional scheme is achieved with a small number of refresh cycles for refreshing all the cells. >

A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's

The feasibility of realizing an emitter-coupled-logic (ECL) interface 4-Mb dynamic RAM (DRAM) with an access time under 10 ns using 0.3- mu m technology is explored, and a deep submicrometer BiCMOS VLSI using this technology is proposed. Five aspects of such a DRAM are covered. They are the internal power supply voltage scheme using on-chip voltage limiters, an ECL DRAM address buffer with a reset function and level converter, a current source for address buffers compensated for device parameter fluctuation, an overdrive rewrite amplifier for realizing a fast cycle time, and double-stage current sensing for the main amplifier and output buffer. Using these circuit techniques, an access time of 7.8 ns is expected with a supply current of 198 mA at a 16-ns cycle time. >

Comparison of CMOS and BiCMOS 1-Mbit DRAM performance

The advantage of BiCMOS technology over CMOS technology in terms of the access time and the power dissipation is demonstrated for a 1.3- mu m 1-Mb DRAM with a TTL (transistor-transistor logic) interface. Two key results are obtained. One is that a BiCMOS driver achieves a 23% lower delay time and 28% lower power dissipation compared with a CMOS driver. This is due to the inherently small input gate capacitance of the BiCMOS inverter and the small number of inverter stages required to make the BiCMOS driver. The other result is that a 1-Mb BiCMOS DRAM incorporating the BiCMOS driver provides higher performance in terms of a 36% faster access time and 24% lower power dissipation after fabrication process deviations and temperature changes. The resistance to the process deviations and temperature changes of the BiCMOS is responsible for such excellent performance. >