Kiyoo Itoh

Trends in low-power RAM circuit technologies

Trends in low-power circuit technologies of CMOS RAM chips are reviewed in terms of three key issues: charging capacitance, operating voltage, and dc current. The discussion includes a general description of power sources in a RAM chip, and covers both DRAMs and SRAMs. In DRAMs, successive circuit advancements have produced a power reduction equivalent to two to three orders of magnitude over the last decade for a fixed memory capacity chip. Coupled with the low-power advantage of CMOS circuits, two technologies have been the major contributors to power reduction: lower charging capacitance due to partial activation of multi-divided arrays that use multi-divisions of data and word lines; and lower operating voltage resulting from external power supply reduction, half-V/sub DD/ precharging and on-chip voltage down converting scheme. In SRAMs, partial activation of a multi-divided word line drastically reduces the dc current from the data-line load to the selected cell. In addition to advances in the sense amplifier circuit, an auto power down scheme that uses address transition detection for word driver and column circuitry further reduces the dc current. It is also shown that to design ultralow voltage DRAMs and SRAMs, the application of subthreshold current reduction circuits (such as source-gate back biasing) to cell and iterative circuit blocks will be indispensable in the future. >

An experimental 1.5-V 64-Mb DRAM

Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V/sub CC/ voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 mu m/sup 2/ crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 mu m electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs. >

Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's

A switched-source-impedance (SSI) CMOS circuit is proposed as a means of reducing the exponential increase of subthreshold current with threshold-voltage scaling. Inserting a switched impedance at the source of a MOS transistor reduces the standby subthreshold current of giga-scale LSIs operating at room temperature by three to four orders of magnitude and suppresses the current variation caused by threshold-voltage and temperature fluctuations. The scheme is applicable to any combinational and sequential CMOS logic circuits as long as their standby node voltages are predictable. The standby current of a 16-Gb DRAM is expected to be reduced from 1.1 A to 0.29 mA using this scheme. Hence, battery backup of giga-scale LSIs will be possible even at room temperature and above. >

Sub-1-V swing internal bus architecture for future low-power ULSIs

A bus architecture is proposed for reducing the operating power of future ULSIs. It uses new types of bus driver circuits and bus receiver circuits to reduce the bus signal swing while maintaining a low standby current. The bus driver circuit has a source offset configuration, achieved by the use of low-V/sub T/ MOSFETs and an internal supply voltage corresponding to the reduced signal swing. The bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of the new bus driver and receiver enables the bus swing to be reduced to one-third that of the conventional architecture while maintaining high-speed data transmission and a low standby current. A test circuit designed and fabricated using 0.3- mu m processes verifies the operation of the proposed architecture. Further improvements in the speed performance are possible with device optimization. >

Crown-shaped stacked-capacitor cell for 1.5-V operation 64-Mb DRAMs

A self-aligned stacked-capacitor cell called the CROWN cell (a crown-shaped stacked-capacitor cell), used for experimental 64-Mb-DRAMs operated at 1.5 V, has been developed using 0.3- mu m electron-beam lithography. This memory cell has an area of 1.28 mu m/sup 2/. The word-line pitch and sense-amplifier pitch of this cell are 0.8 and 1.6 mu m, respectively. In spite of this small cell area, the CROWN cell has a large capacitor surface area of 3.7 mu m/sup 2/ because (1) it has a crown-shaped capacitor electrode, (2) its capacitor is on the data line, and (3) it has a self-aligned memory cell fabrication process and structure. The large capacitor area and a Ta/sub 2/O/sub 5/ film equivalent to a 2.8-nm SiO/sub 2/ film ensure a large storage charge of 33 fC (storage capacitance equals 44 fF) for 1.5-V operation. A small CROWN cell array and a memory test circuit were successfully used to achieve a basic DRAM cell operation. >

A deep sub-V, single power-supply SRAM cell with multi-V/sub T/, boosted storage node and dynamic load

The key issues in ultralow voltage SRAM design are a reduction in power supply voltage to a solar-cell voltage of 0.5V or less, single supply operation, and an increase in the cell voltage-margin. However, these problems remain largely unsolved. Even in most advanced cells an unavoidably high FET threshold voltage (V/sub T/) of the cell compared with the low stored node-voltage of supply restricts the supply to around 1V, although 0.5 V operation has been reported with no cell margin. Moreover, the negative pull down of the cell source line prevents single supply operation, since an on-chip negative voltage generator comprising charge pumping circuits never manages a heavy data-line capacitance. This paper describes an innovative circuit for overcoming these problems, demonstrating the feasibility of a single 0.3 V, 50 MHz, 0.25 /spl mu/m 8Kb SRAM. A multi-V/sub T/ cell, a boosted cell storage-node and a dynamic cell load contribute to the outstanding performance.

Limitations and challenges of multigigabit DRAM chip design

This paper describes the limitations and challenges involved in designing gigabit DRAM chips in terms of high-density devices, high-performance circuits, and low-power/low-voltage circuits. The key results obtained are as follows. 1) For formation of a MOSFET shallow junction, which suppresses threshold voltage (V/sub T/) variation and offset voltage of sense amplifiers, reduction in ion-implantation energy and process temperature is essential. Also, the keys in terms of area, speed, stable cell operation, and ease of fabrication are use of low-resistivity multilevel metal wiring and high permittivity materials and three-dimensional memory cells to reduce a difference in height between the memory cell array and the surrounding peripheral circuits. 2) For creation of a high speed, the keys are memory-subsystem technology such as pipeline operation, wide-bit I/O, low-voltage interfaces, and high-density packaging. Embedded DRAM further enhances the speed and throughput by using massively parallel processing of signals on a large number of data-lines and reducing internal bus capacitances. 3) For power reduction, the key continues to be reduction of the data-line dissipating charge through both partial activation of multidivided data-lines and lowering of the data-line voltage. Ultralow-voltage operation, essential to drastic power reduction, can be achieved by subthreshold-current reduction circuits such as source-gate backbiasing, multi-V/sub T/, dynamic V/sub T/, and node-boosting schemes.

An experimental 1Mb DRAM with on-chip voltage limiter

This paper will report on an experimental 21μm²cell, single 5V 1Mb NMOS DRAM. Typical clata are: access time 90ns, power dissipation 300mW at 260ns cycle time. Chip area is 46mm²

Trends in megabit DRAM circuit design

The state of the art in megabit dynamic random access memory (DRAM) circuit and chip design is reviewed in terms of essential design parameters such as signal-to-noise ratio, power dissipation, and speed. The memory cell signal charge has decreased gradually with an increase in memory cell size, despite the vertically structured cell designs. To offset this decrease, multidivided data-line structures, low-power design, and transposition of folded data lines are essential. To reduce power dissipation, an increase in the maximum refresh cycle and multidivided data lines combined with shared I/O in addition to a reduced operating voltage are efficient. A BiCMOS circuit provides a high-speed access time with low cost due to the high drivability of the driver and high sensitivity of the amplifier. It is predicted that the current DRAM technology might be diversified in the future so that a large-memory-capacity-oriented technology would coexist with a high-speed-oriented technology, posing power-supply standardization as a continuing serious concern. >

Subthreshold-current reduction circuits for multi-gigabit DRAM's

Two subthreshold-current reduction circuit schemes are described to suppress the increase in current in multi-gigabit DRAMs. One is a hierarchical power-line scheme for iterative circuits. In this scheme, a group of circuits is divided into blocks; only the selected block is supplied with power, while the subthreshold current to the many nonselected blocks is reduced. This scheme minimizes the number of circuits carrying the large subthreshold current. Applications of this scheme to word drivers, decoders and sense-amplifier driving circuits are shown. The other scheme is a switched-power-supply inverter with a level holder for random combinational logic circuits. In the active mode of the chip, the operating period of the inverter is distinguished from the inactive period. The inverter is supplied with power only in the operating period, while in the inactive period the subthreshold current is shut off and the output level is kept by the flip-flop level holder. This scheme shortens the period in which the large subthreshold current flows. Both schemes are evaluated for a conceptually-designed 16-Gb DRAM. They reduce its active current by ten-fold from the conventional 1.2 A to 116 mA. >