Götz Kappen

Application specific instruction processor based implementation of a GNSS receiver on an FPGA

In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in low-power, low-cost SoC for multioperable GNSS positioning is described, featuring sufficient computational power and flexibility. The central processing unit of the reconfigurable hardware macro is an ASIP accelerated by additional eFPGA and weakly configurable ASIC based co-processors. The different hardware building blocks (i.e. ASIP, eFPGA, ASIC) of the target architecture are motivated with state of the art GNSS receiver algorithms. To explore the design space of the target architecture and to develop appropriate partitioning cost functions a GNSS receiver testbed was realised on an FPGA board. The testbed utilises a programmable ASIP, designed and generated with the processor description language LISA, as a central processing unit. As a first accelerating co-processor the correlator was realised. Exemplary optimisations of the ASIP/co-processor architecture as well as the achieved improvements are described

An architecture for an embedded antenna-array digital GNSS receiver using subspace-based methods for spatial filtering

This paper presents an architecture for an embedded multi-antenna digital GNSS receiver. A two-stage adaptive beamformer for interference suppression and Line-of-Sight (LoS) signal amplification is presented and analyzed w.r.t. to an efficient implementation on embedded receivers. Jammer signals are mitigated at pre-correlation stage whereas the LoS signals are amplified at post-correlation stage. The method is based on a subspace-based approach where filter coefficients are derived from the eigenvalues and -vectors of the covariance matrix. In the first stage, the covariance matrix is determined immediately from the digital antenna signals for interference mitigation and in the second stage, the matrix is computed based on the correlator outputs of each satellite in LoS. Dedicated buildingblocks for covariance matrix estimation and filtering are required for interference mitigation since this operation is computed on sampling rate. A fixed-point VHDL implementation and related costs in terms of logic-cell requirements on an FPGA are provided for both blocks. Eigendecomposition is computed on an embedded processor. The implementation of two decomposition algorithms (one for interference mitigation and the other one for LoS-signal amplification) are presented. Optimizations and costs in terms of processing-cycles on an embedded processor are provided.

Reconfigurable Components for Application-Specific Processor Architectures

Embedded Field Programmable Gate Arrays feature very attractive properties for their use as building blocks of future heterogeneous Systems-on-Chip. In this Chapter strategies are described how to achieve those reconfigurable System-on-Chip components with high energy and area efficiencies. One of the basic ideas is to leverage a-priori knowledge about the structures to be implemented on those arrays to optimize them for classes of applications. This leads to a parameterized target architecture which allows for dedicated adaptation to certain instances on a System-on-Chip. A design flow suitable in a research environment is described. For applications of digital arithmetic, e.g. in digital signal processing, it will be shown how this approach works. As an especially attractive application the use of those components as coprocessors to Application Specific Instruction Processors can be identified. Suitable architectures of such combinations and the resulting features are investigated.

Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers

The development of algorithms from the communication and the signal processing domain often requires floating point arithmetic as well as support for trigonometric functions. While state-of-the-art digital signal processors offer hardware support for this kind of functions, embedded processors for mobile applications emulate floating point arithmetic and trigonometric functions in software. This emulation increases the number of required processing cycles compared to a dedicated hardware implementation. During development and implementation of ASIPs another problem with the emulation of these instructions arises. As the emulation has to be very flexible (e.g. variable operand bit width) emulation is carried out generally in a high level programming language leading to increased flexibility at the cost of reduced performance. This paper presents the design space exploration for an ASIP with an attached floating point co-processor in terms of performance and area and energy costs. To integrate the co-processor instructions, the ASIP’s architecture description is modified and software development tools (e.g. assembler, linker and compiler) are adapted. Additionally, the ASIP’s software libraries allow for a seamless integration of the co-processor instructions and enable ease of use for the application development. Power consumption and required silicon area can be decreased by choosing an application specific subset of supported co-processor functions and reduction of the co-processor’s datapath bit width. The presented ASIP/co-processor architecture is functionally verified and area and power figures are derived for various configurations. A detailed analysis of the presented architecture used as a platform for GNSS receivers reveals promising configurations.

ASIP-eFPGA Architecture for Multioperable GNSS Receivers

In this paper a novel flexible architecture exemplarily applied for multioperable GNSS receivers including an ASIP and an arithmetic oriented embedded FPGA is presented. The advent of next generation GNSS-systems as well as different demands in different system phases require high flexibility. The proposed architecture provides high energy and area efficiency compared to software-programmable processor while preserving flexibility. Exemplarily the mapping of the computational intensive base band processing of a Navstar GPS receiver to an ASIP-eFPGA architecture will be discussed. Results are based on a standard cell based design regarding the ASIP. A design method for physically optimized VLSI-macros has been applied for the implementation of the eFPGA. All results are acquired for a 90 nm-CMOS technology. It will be shown that the proposed heterogeneous architecture features an attractive position in the design space regarding area and energy efficiency as well as flexibility.

Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers

This paper presents the enhancement of an ASIPs floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications and subsequent adaptation of software development tools (e.g. assembler, linker and compiler) are described. Additionally, this work focuses on seamless integration of the co-processor to enable ease of use for the application development. Power consumption and silicon area of the co-processor can be reduced by choosing an application specific subset of functions. Hardware description files of ASIP and co-processor are used for functional verification and processing cycle determination. Area and power estimation of the overall architecture is presented for a 90 nm standard cell CMOS technology. Finally, a design space exploration of the presented architecture used in a satellite navigation receiver reveals efficient co-processor configurations.

Potential of using block floating point arithmetic in ASIP-based GNSS-receivers

As an alternative to floating point and fixed point arithmetics, block floating point arithmetic offers a compromise between computational accuracy and hardware complexity. Nevertheless, today practical applications are limited to Fast Fourier Transformation and digital filters. This work uses the block floating point format to realize the position estimation algorithm in Global Navigation Satellite System (GNSS) receivers, which is based on the Newton-Rhapson method. The precision of this novel approach is quantified by extensive simulations using synthetic as well as real GNSS data. The implementation of the position estimation algorithm using block floating point format on an application specific processor is introduced and compared to implementations on a standard embedded processor and in standard floating point arithmetic in terms of performance and costs.

SPP1148 booth: Application-specific reconfigurable processors

Application-specific reconfigurable processor architectures provide a remarkable potential for systems which achieve concurrently high performance, area efficiency, energy efficiency, run-time adaptivity, and sufficient flexibility. Thus, they represent competitive design alternatives that provide significant improvements in some of these figures of merit in comparison to non-reconfigurable architectures. Research results of three projects on the analysis of architecture concepts, design, and evaluation of application-specific reconfigurable processors in different domains are presented.