Greg Dunne

Reliability Issues of SiC MOSFETs: A Technology for High-Temperature Environments

The wide-bandgap nature of silicon carbide (SiC) makes it an excellent candidate for applications where high temperature is required. The metal-oxide-semiconductor (MOS)-controlled power devices are the most favorable structure; however, it is widely believed that silicon oxide on SiC is physically limited, particularly at high temperatures. Therefore, experimental measurements of long-term reliability of oxide at high temperatures are necessary. In this paper, time-dependent dielectric-breakdown measurements are performed on state-of-the-art 4H-SiC MOS capacitors and double-implanted MOS field-effect transistors (DMOSFET) with stress temperatures between 225°C and 375°C and stress electric fields between 6 and 10 MV/cm. The field-acceleration factor is around 1.5 dec/(MV/cm) for all of the temperatures. The thermal activation energy is found to be ~ 0.9 eV, independent of the electric field. The area dependence of Weibull slope is discussed and shown to be a possible indication that the oxide quality has not reached the intrinsic regime and further oxide-reliability improvements are possible. Since our reliability data contradict the widely accepted belief that silicon oxide on SiC is fundamentally limited by its smaller conduction-band offset compared with Si, a detailed discussion is provided to examine the arguments of the early predictions.

Physical Vapor Transport Growth and Properties of SiC Monocrystals of 4H Polytype

The physical vapor transport technique can be employed to fabricate large diameter silicon carbide crystals (up to 50 mm diameter) exhibiting uniform 4H-polytype over the full crystal volume. Crystal growth rate is controlled to first order by temperature conditions and ambient pressure. 4H-polytype uniformity is controlled by polarity of the seed crystal and the growth temperature. 4H-SiC crystals exhibit crystalline defects mainly in the form of dislocations with densities in the 10 4 cm -2 range and micropipe defects, the latter having densities as low as 10 cm -2 in best crystals. Electrical conductivity in 4H-SiC bulk crystals ranges from 10 15 Ω cm) at room temperature.

Demonstration of ultraviolet separate absorption and multiplication 4H-SiC avalanche photodiodes

We report ultraviolet separate absorption and multiplication 4H-SiC avalanche photodiodes. An external quantum efficiency of 83% (187 mA/W) at 278 nm, corresponding to unity gain after reach-through was achieved. A gain higher than 1000 was demonstrated without edge breakdown.

Time-Dependent Dielectric Breakdown of 4H-SiC MOS Capacitors and DMOSFETs

Time-dependent dielectric breakdown measurements were performed at 200 degC on 4H-SiC MOS capacitors and vertical DMOSFETs with 50-nm-thick nitrided oxides in order to better understand the physical mechanisms of failure and to predict the component reliability. Oxide breakdown locations are shown to have no correlation to defects in the SiC epitaxial layer. Characterization of the electric-field acceleration of failures indicates that failure modes differ at low and high electric fields. Specifically, extrapolations from measurements at electric fields greater than 8.5 MV/cm predict anomalously high reliability at normal operating fields. Thus, we have shown that SiC MOS reliability characterization must ensure that electric field stresses be performed at low electric fields in order to accurately predict failure times.

Electron-Scattering Mechanisms in Heavily Doped Silicon Carbide MOSFET Inversion Layers

Hall-effect measurements of n-channel MOS devices were used to determine the main scattering mechanisms limiting mobility in SiC MOSFETs. MOS-gated Hall characterization, which was performed as a function of gate bias and body bias, indicates that surface-roughness scattering and Coulomb scattering are the main scattering mechanisms limiting electron mobility in SiC MOSFETs at room temperature. A charge-sheet model, including incomplete ionization and Fermi-Dirac statistics, is used to calculate the surface electric fields in order to develop an expression for surface-roughness scattering. In the samples used for this paper, at electron sheet densities less than 1.8times1012 cm-2, Coulomb scattering dominates, while surface roughness is dominant at higher sheet densities.

Comparison of metal-oxide-semiconductor capacitors on c- and m-plane gallium nitride

The properties of the SiO2∕GaN interface were characterized using metal-oxide-semiconductor capacitors on polar c-plane (0001) and nonpolar m-plane (0 1 -1 0) GaN crystal faces. GaN m-plane samples show the absence of pyroelectric polarization effects. Additionally, capacitance-voltage hysteresis is less on m-plane compared to c-plane GaN surfaces, suggesting a lower interface-state density at the m-plane GaN∕SiO2 interface.

Trap and Inversion Layer Mobility Characterization Using Hall Effect in Silicon Carbide-Based MOSFETs With Gate Oxides Grown by Sodium Enhanced Oxidation

Low-temperature MOS-gated Hall measurements and gated diode capacitance-voltage (C-V) measurements were performed to characterize both trap density and Hall mobility on 4H-silicon carbide MOSFETs with gate oxides grown by sodium enhanced oxidation (SEO) and thermally grown in N2O. The interface trap density Dit was determined close to the conduction band edge by Hall effect measurements to be 2?1013 cm-2 ? eV-1 in the N2O-based oxide sample and 1?1011 cm-2 ? eV-1 in the SEO sample. The presence of these interface trap states above the conduction band edge suggest that they are near interface oxide trap states rather than conventional fast interface trap states. The threshold voltage changes with temperature in MOSFETs with gate oxides grown thermally with N2O but not significantly in MOSFETs with gate oxides grown by SEO. The superior threshold voltage stability at low temperatures in the SEO-based MOSFET compared to the N2O oxidation-based MOSFET is due to lower trap density near the conduction band edge. Gated diode C-V measurements showed that MOSFETs with gate oxide grown by SEO had a higher density of interface traps (2.2?1012 cm-2) deeper in the bandgap compared to MOSFETs with gate oxides thermally grown in N2O (1.4?1012 cm-2). A maximum Hall mobility of 65 cm2/V ? s was measured in the SEO-based MOSFET, and 16 cm2/V ? s was measured on the N2O oxidation-based MOSFET at 225 K. The mobility correlates well with the interface trap density close to the conduction band edge as measured by Hall effect measurements but does not correlate with gated diode C-V measurements of traps deeper in the band gap. Temperature-dependent gated Hall mobility measurements were used to show that the inversion layer mobility in the SEO samples were limited by Coulomb scattering from interface trapped charge and surface roughness scattering but not by phonon scattering.

Time-Dependent Dielectric Breakdown of 4H-SiC/

Time-dependent dielectric breakdown (TDDB) is one of the major issues concerning long-range reliability of dielectric layers in SiC-based high-power devices. Despite the extensive research on TDDB of SiO2 layers on Si, there is a lack of high-quality statistical TDDB data of SiO2 layers on SiC. This paper presents comprehensive TDDB data of 4H-SiC capacitors with a SiO2 gate insulator collected over a wide range of electric fields and temperatures. The results show that at low fields, the electric field acceleration parameter is between 2.07 and 3.22 cm/MV. At fields higher than 8.5 MV/cm, the electric field acceleration parameter is about 4.6 cm/MV, indicating a different failure mechanism under high electric field stress. Thus, lifetime extrapolation must be based on failure data collected below 8.5 MV/cm. Temperature acceleration follows the Arrhenius model with activation energy of about 1 eV, similar to thick SiO2 layers on Si. Based on these experimental data, we propose an accurate model for lifetime assessment of 4H-SiC MOS devices considering electric field and temperature acceleration, area, and failure rate percentile scaling. It is also demonstrated that temperatures as high as 365degC can be used to accelerate TDDB of SiC devices at the wafer level.

\hbox{SiO}_{2}

SiC vapor-phase epitaxy on porous silicon carbide (PSC) substrates formed by electrochemical anodization is reported. Raman scattering indicates that the polytype of the optically smooth SiC grown on PSC formed in both p-type and n-type 6H substrates is 6H. The Raman scattering selection rules in these films are the same as those observed in the bulk substrate and epilayers grown on bulk, indicating high crystalline quality. The formation of epitaxial 6H–SiC on porous 6H–SiC may open up new possibilities for dielectric device isolation, fabrication, and epitaxial lift-off.

MOS Capacitors

We address the two critical challenges that currently limit the applicability of SiC MOSFETs in commercial power conversion systems: high-temperature gate oxide reliability and high total current rating. We demonstrate SiC MOSFETs with predicted gate oxide reliability of >106 hours (100 years) operating at a gate oxide electric field of 4 MV/cm at 250°C. To scale to high total currents, we develop the Power Overlay planar packaging technique to demonstrate SiC MOSFET power modules with total on-resistance as low as 7.5 m. We scale single die SiC MOSFETs to high currents, demonstrating a large area SiC MOSFET (4.5mm x 4.5 mm) with a total on-resistance of 30 m, specific on-resistance of 5 m-cm2 and blocking voltage of 1400V.