Kevin Matocha

High-voltage normally off GaN MOSFETs on sapphire substrates

Gallium nitride self-aligned MOSFETs were fabricated using low-pressure chemical vapor-deposited silicon dioxide as the gate dielectric and polysilicon as the gate material. Silicon was implanted into an unintentionally doped GaN layer using the polysilicon gate to define the source and drain regions, with implant activation at 1100/spl deg/C for 5 min in nitrogen. The GaN MOSFETs have a low gate leakage current of less than 50 pA for circular devices with W/L=800/128 /spl mu/m. Devices are normally off with a threshold voltage of +2.7 V and a field-effect mobility of 45 cm/sup 2//Vs at room temperature. The minimum on-resistance measured is 1.9 m/spl Omega//spl middot/cm/sup 2/ with a gate voltage of 34 V (W/L=800/2 /spl mu/m). High-voltage lateral devices had a breakdown voltage of 700 V with gate-drain spacing of 9 /spl mu/m (80 V//spl mu/m), showing the feasibility of self-aligned GaN MOSFETs for high-voltage integrated circuits.

Reliability Issues of SiC MOSFETs: A Technology for High-Temperature Environments

The wide-bandgap nature of silicon carbide (SiC) makes it an excellent candidate for applications where high temperature is required. The metal-oxide-semiconductor (MOS)-controlled power devices are the most favorable structure; however, it is widely believed that silicon oxide on SiC is physically limited, particularly at high temperatures. Therefore, experimental measurements of long-term reliability of oxide at high temperatures are necessary. In this paper, time-dependent dielectric-breakdown measurements are performed on state-of-the-art 4H-SiC MOS capacitors and double-implanted MOS field-effect transistors (DMOSFET) with stress temperatures between 225°C and 375°C and stress electric fields between 6 and 10 MV/cm. The field-acceleration factor is around 1.5 dec/(MV/cm) for all of the temperatures. The thermal activation energy is found to be ~ 0.9 eV, independent of the electric field. The area dependence of Weibull slope is discussed and shown to be a possible indication that the oxide quality has not reached the intrinsic regime and further oxide-reliability improvements are possible. Since our reliability data contradict the widely accepted belief that silicon oxide on SiC is fundamentally limited by its smaller conduction-band offset compared with Si, a detailed discussion is provided to examine the arguments of the early predictions.

Recent advances in silicon carbide MOSFET power devices

Emerging silicon carbide (SiC) MOSFET power devices promise to displace silicon IGBTs from the majority of challenging power electronics applications by enabling superior efficiency and power density, as well as capability to operate at higher temperatures. This paper reports on the recent progress in development of 1200V SiC power MOSFETs. Two different chip sizes were fabricated and tested: 15A (0.225cm×0.45cm) and 30A (0.45cm×0.45cm) devices. First, the 30A MOSFETs were packaged as discrete components and static and switching measurements were performed. The device blocking voltage was 1200V and typical on-resistance was less than 50 mΩ with gate-source voltages of 0V and 20V, respectively. The total switching losses were 0.6 mJ, over five times lower than the competing devices. Next, a buck converter was built for evaluating long-term stability of the MOSFETs and typical switching waveforms are presented. Finally, the 15A MOSFETs were used for fabrication of 150A all-SiC modules. The module on-resistance values were in the range of 10 mQ, resulting in the best-in-class on-state voltage values of 1.5V at nominal current. The module switching losses were 2.3 mJ during turn-on and 1 mJ during turn-off, also significantly better than competing designs. The results validate performance advantages of the SiC MOSFETs, moving them a step closer to power electronics applications.

Direct comparison of silicon and silicon carbide power transistors in high-frequency hard-switched applications

RECENT progress in wide bandgap power (WBG) switches shows great potential. Silicon carbide (SiC) is a promising material for power devices with breakdown voltages of several hundred volts up to 10 kV. SiC Schottky power diodes have achieved widespread commercial acceptance. Recently, much progress has been made on active SiC switches, including JFETs, thyristors, BJTs, IGBTs, and MOSFETs. Many a great promise has been made, and wondrous claims abound, but the question remains: will they live up to the hype? We explore this question for the class of high-frequency, hard-switched converters with input voltages of up to 600 VDC and power throughputs in the kilowatt range. Experimental evidence shows that both superior efficiency and higher power density may be obtained via the use of SiC MOSFETs. A direct comparison is made using silicon power devices (IGBTs and MOSFETs) and SiC MOSFETs in a 200 kHz, 6 kW, 600 V hard-switched converter. The losses are measured and conduction and switching losses of the active devices are estimated. Total losses can be reduced by a factor of 2–5 by substitution of SiC MOSFETs for Si active power devices.

Time-Dependent Dielectric Breakdown of 4H-SiC MOS Capacitors and DMOSFETs

Time-dependent dielectric breakdown measurements were performed at 200 degC on 4H-SiC MOS capacitors and vertical DMOSFETs with 50-nm-thick nitrided oxides in order to better understand the physical mechanisms of failure and to predict the component reliability. Oxide breakdown locations are shown to have no correlation to defects in the SiC epitaxial layer. Characterization of the electric-field acceleration of failures indicates that failure modes differ at low and high electric fields. Specifically, extrapolations from measurements at electric fields greater than 8.5 MV/cm predict anomalously high reliability at normal operating fields. Thus, we have shown that SiC MOS reliability characterization must ensure that electric field stresses be performed at low electric fields in order to accurately predict failure times.

Electron-Scattering Mechanisms in Heavily Doped Silicon Carbide MOSFET Inversion Layers

Hall-effect measurements of n-channel MOS devices were used to determine the main scattering mechanisms limiting mobility in SiC MOSFETs. MOS-gated Hall characterization, which was performed as a function of gate bias and body bias, indicates that surface-roughness scattering and Coulomb scattering are the main scattering mechanisms limiting electron mobility in SiC MOSFETs at room temperature. A charge-sheet model, including incomplete ionization and Fermi-Dirac statistics, is used to calculate the surface electric fields in order to develop an expression for surface-roughness scattering. In the samples used for this paper, at electron sheet densities less than 1.8times1012 cm-2, Coulomb scattering dominates, while surface roughness is dominant at higher sheet densities.

First-principles-based investigation of kinetic mechanism of SiC(0001) dry oxidation including defect generation and passivation

The key stages of the dry oxidation of the SiC(0001) surface are analyzed based on first-principles calculations. It is found that an abrupt SiC/SiO2 interface model results in a large activation barrier of oxygen penetration to the silicon carbide, and thus the penetration is probably the rate-limiting step for the entire dry-oxidation process. The subsequent reactions of SiC oxidation after oxygen penetration are investigated, and it is found that CO release is competing with carbon dimer formation. These dimers probably are responsible for near-interface traps in the silica layer generated during SiC oxidation. The possible passivation reactions of a carbon dimer defect by active species, such as O2, NO, and H2 are investigated. It is found that an oxygen molecule can break a Si–C bond via dissociation in the triplet state and finally can produce two CO molecules from the carbon dimer defect. The NO molecule can easily break a Si–C bond of a carbon dimer defect and form cyano groups –CN, which can fina...

Comparison of metal-oxide-semiconductor capacitors on c- and m-plane gallium nitride

The properties of the SiO2∕GaN interface were characterized using metal-oxide-semiconductor capacitors on polar c-plane (0001) and nonpolar m-plane (0 1 -1 0) GaN crystal faces. GaN m-plane samples show the absence of pyroelectric polarization effects. Additionally, capacitance-voltage hysteresis is less on m-plane compared to c-plane GaN surfaces, suggesting a lower interface-state density at the m-plane GaN∕SiO2 interface.

Trap and Inversion Layer Mobility Characterization Using Hall Effect in Silicon Carbide-Based MOSFETs With Gate Oxides Grown by Sodium Enhanced Oxidation

Low-temperature MOS-gated Hall measurements and gated diode capacitance-voltage (C-V) measurements were performed to characterize both trap density and Hall mobility on 4H-silicon carbide MOSFETs with gate oxides grown by sodium enhanced oxidation (SEO) and thermally grown in N2O. The interface trap density Dit was determined close to the conduction band edge by Hall effect measurements to be 2?1013 cm-2 ? eV-1 in the N2O-based oxide sample and 1?1011 cm-2 ? eV-1 in the SEO sample. The presence of these interface trap states above the conduction band edge suggest that they are near interface oxide trap states rather than conventional fast interface trap states. The threshold voltage changes with temperature in MOSFETs with gate oxides grown thermally with N2O but not significantly in MOSFETs with gate oxides grown by SEO. The superior threshold voltage stability at low temperatures in the SEO-based MOSFET compared to the N2O oxidation-based MOSFET is due to lower trap density near the conduction band edge. Gated diode C-V measurements showed that MOSFETs with gate oxide grown by SEO had a higher density of interface traps (2.2?1012 cm-2) deeper in the bandgap compared to MOSFETs with gate oxides thermally grown in N2O (1.4?1012 cm-2). A maximum Hall mobility of 65 cm2/V ? s was measured in the SEO-based MOSFET, and 16 cm2/V ? s was measured on the N2O oxidation-based MOSFET at 225 K. The mobility correlates well with the interface trap density close to the conduction band edge as measured by Hall effect measurements but does not correlate with gated diode C-V measurements of traps deeper in the band gap. Temperature-dependent gated Hall mobility measurements were used to show that the inversion layer mobility in the SEO samples were limited by Coulomb scattering from interface trapped charge and surface roughness scattering but not by phonon scattering.

Time-Dependent Dielectric Breakdown of 4H-SiC/

Time-dependent dielectric breakdown (TDDB) is one of the major issues concerning long-range reliability of dielectric layers in SiC-based high-power devices. Despite the extensive research on TDDB of SiO2 layers on Si, there is a lack of high-quality statistical TDDB data of SiO2 layers on SiC. This paper presents comprehensive TDDB data of 4H-SiC capacitors with a SiO2 gate insulator collected over a wide range of electric fields and temperatures. The results show that at low fields, the electric field acceleration parameter is between 2.07 and 3.22 cm/MV. At fields higher than 8.5 MV/cm, the electric field acceleration parameter is about 4.6 cm/MV, indicating a different failure mechanism under high electric field stress. Thus, lifetime extrapolation must be based on failure data collected below 8.5 MV/cm. Temperature acceleration follows the Arrhenius model with activation energy of about 1 eV, similar to thick SiO2 layers on Si. Based on these experimental data, we propose an accurate model for lifetime assessment of 4H-SiC MOS devices considering electric field and temperature acceleration, area, and failure rate percentile scaling. It is also demonstrated that temperatures as high as 365degC can be used to accelerate TDDB of SiC devices at the wafer level.